On Thu, Apr 10, 2014 at 05:24:36PM -0700, Matt Roper wrote: > Intel hardware allows the primary plane to be disabled independently of > the CRTC. Provide custom primary plane handling to allow this. > > v2: > - Unpin fb properly on primary plane disable > - Provide an Intel-specific set of primary plane formats > - Additional sanity checks on setplane (in line with the checks > currently being done by the DRM core primary plane helper) > > Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx> > --- > > This patch was previously part of my universal plane series on dri-devel > (http://lists.freedesktop.org/archives/dri-devel/2014-March/055852.html) but I > dropped it in v4 and v5 of that series to focus on the DRM core changes. Now > that universal planes have been merged, we can start building on that framework > to provide i915-specific functionality. > > Some i-g-t changes to test this will be sent shortly. > > > Matt > > > drivers/gpu/drm/i915/intel_display.c | 165 ++++++++++++++++++++++++++++++++++- > drivers/gpu/drm/i915/intel_drv.h | 1 + > 2 files changed, 164 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 1af1d14..a0bc251 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -39,8 +39,24 @@ > #include "i915_trace.h" > #include <drm/drm_dp_helper.h> > #include <drm/drm_crtc_helper.h> > +#include <drm/drm_rect.h> > #include <linux/dma_remapping.h> > > +const static uint32_t intel_primary_formats[] = { > + DRM_FORMAT_C8, > + DRM_FORMAT_XRGB1555, > + DRM_FORMAT_ARGB1555, > + DRM_FORMAT_RGB565, > + DRM_FORMAT_XRGB8888, > + DRM_FORMAT_ARGB8888, > + DRM_FORMAT_XBGR8888, > + DRM_FORMAT_ABGR8888, > + DRM_FORMAT_XRGB2101010, > + DRM_FORMAT_ARGB2101010, > + DRM_FORMAT_XBGR2101010, > + DRM_FORMAT_ABGR2101010, > +}; I think going the extra step and having correct per-gen format lists would be good. See intel_framebuffer_init for which platfrom can do what. Unfortunately we can't yet change those checks to WARNs since the core doesn't yet check the primary plane format against this list ... And we can't do that yet since not all drivers are converted yet to have at least an explicit format list :( > + > static void intel_increase_pllclock(struct drm_crtc *crtc); > static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); > > @@ -10553,17 +10569,162 @@ static void intel_shared_dpll_init(struct drm_device *dev) > BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); > } > > +static int > +intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc, > + struct drm_framebuffer *fb, int crtc_x, int crtc_y, > + unsigned int crtc_w, unsigned int crtc_h, > + uint32_t src_x, uint32_t src_y, > + uint32_t src_w, uint32_t src_h) > +{ > + struct drm_device *dev = crtc->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > + struct drm_framebuffer *tmpfb; > + struct drm_rect dest = { > + .x1 = crtc_x, > + .y1 = crtc_y, > + .x2 = crtc_x + crtc_w, > + .y2 = crtc_y + crtc_h, > + }; > + struct drm_rect clip = { > + .x2 = crtc->mode.hdisplay, > + .y2 = crtc->mode.vdisplay, > + }; > + int ret; > + > + /* setplane API takes shifted source rectangle values; unshift them */ > + src_x >>= 16; > + src_y >>= 16; > + src_w >>= 16; > + src_h >>= 16; > + > + /* > + * Current hardware can't reposition the primary plane or scale it > + * (although this could change in the future). > + */ > + drm_rect_intersect(&dest, &clip); > + if (dest.x1 != 0 || dest.y1 != 0 || > + dest.x2 != crtc->mode.hdisplay || dest.y2 != crtc->mode.vdisplay) { > + DRM_DEBUG_KMS("Primary plane must cover entire CRTC\n"); > + return -EINVAL; > + } > + > + if (crtc_w != src_w || crtc_h != src_h) { > + DRM_DEBUG_KMS("Can't scale primary plane\n"); > + return -EINVAL; > + } Subpixel check seems to be missing. And can't we extract all these checks both here and from the primary plane helper? I guess there'll be other hw which doesn't have scaling primary planes, but which wants to allow primary plane enable/disable. > + > + /* Primary planes are locked to their owning CRTC */ > + if (plane->possible_crtcs != drm_crtc_mask(crtc)) { > + DRM_DEBUG_KMS("Cannot change primary plane CRTC\n"); > + return -EINVAL; > + } > + > + /* Framebuffer must be big enough to cover entire plane */ > + ret = drm_crtc_check_viewport(crtc, crtc_x, crtc_y, &crtc->mode, fb); > + if (ret) > + return ret; > + > + /* > + * pipe_set_base() adjusts crtc->primary->fb; however the DRM setplane > + * code that called us expects to handle the framebuffer update and > + * reference counting; save and restore the current fb before > + * calling it. > + */ > + tmpfb = plane->fb; > + ret = intel_pipe_set_base(crtc, src_x, src_y, fb); > + if (ret) > + return ret; > + plane->fb = tmpfb; > + > + if (!intel_crtc->primary_enabled) > + intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, > + intel_crtc->pipe); Hm, I've thought we could do a simple if (intel_crtc->primary_enabled) call_primary_plane_helper else enable_the_hw_plane But we need to do all the arg checking for the !primary_enabled case :( Anyway more code sharing make me happier. Cheers, Daniel > + > + return 0; > +} > + > +static int > +intel_primary_plane_disable(struct drm_plane *plane) > +{ > + struct drm_device *dev = plane->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_plane *intel_plane = to_intel_plane(plane); > + struct intel_crtc *intel_crtc; > + > + if (!plane->fb) > + return 0; > + > + if (WARN_ON(!plane->crtc)) > + return -EINVAL; > + > + intel_crtc = to_intel_crtc(plane->crtc); > + if (intel_crtc->primary_enabled) > + intel_disable_primary_hw_plane(dev_priv, intel_plane->plane, > + intel_plane->pipe); > + > + /* > + * N.B. The DRM setplane code will update the plane->fb pointer after > + * we finish here. > + */ > + intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj); > + > + return 0; > +} > + > +static void intel_primary_plane_destroy(struct drm_plane *plane) > +{ > + struct intel_plane *intel_plane = to_intel_plane(plane); > + intel_primary_plane_disable(plane); > + drm_plane_cleanup(plane); > + kfree(intel_plane); > +} > + > +static const struct drm_plane_funcs intel_primary_plane_funcs = { > + .update_plane = intel_primary_plane_setplane, > + .disable_plane = intel_primary_plane_disable, > + .destroy = intel_primary_plane_destroy, > +}; > + > +static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, > + int pipe) > +{ > + struct intel_plane *primary; > + > + primary = kzalloc(sizeof(*primary), GFP_KERNEL); > + if (primary == NULL) > + return NULL; > + > + primary->can_scale = false; > + primary->pipe = pipe; > + primary->plane = pipe; > + > + drm_plane_init(dev, &primary->base, 0, > + &intel_primary_plane_funcs, intel_primary_formats, > + ARRAY_SIZE(intel_primary_formats), > + DRM_PLANE_TYPE_PRIMARY); > + return &primary->base; > +} > + > static void intel_crtc_init(struct drm_device *dev, int pipe) > { > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc; > - int i; > + struct drm_plane *primary; > + int i, ret; > > intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); > if (intel_crtc == NULL) > return; > > - drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); > + primary = intel_primary_plane_create(dev, pipe); > + ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, > + NULL, &intel_crtc_funcs); > + if (ret) { > + drm_crtc_cleanup(&intel_crtc->base); > + kfree(intel_crtc); > + return; > + } > > drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); > for (i = 0; i < 256; i++) { > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index c551472..2ce9cc3 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -363,6 +363,7 @@ struct intel_crtc { > bool active; > unsigned long enabled_power_domains; > bool eld_vld; > + struct intel_plane *primary_plane; > bool primary_enabled; /* is the primary plane (partially) visible? */ > bool lowfreq_avail; > struct intel_overlay *overlay; > -- > 1.8.5.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
