From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
We need to pick the correct data lanes based on the port not the
pipe, so move the data lane deassert into the encoder .pre_enable()
hook from the chv_enable_pll().
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_display.c | 5 -----
drivers/gpu/drm/i915/intel_dp.c | 9 ++++++++-
drivers/gpu/drm/i915/intel_hdmi.c | 8 +++++++-
3 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d531c9d..39be658 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1588,11 +1588,6 @@ static void chv_enable_pll(struct intel_crtc *crtc)
I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
POSTING_READ(DPLL_MD(pipe));
- /* Deassert soft data lane reset*/
- tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
- tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
- vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
-
mutex_unlock(&dev_priv->dpio_lock);
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7c4047b..ad56cac 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1950,9 +1950,16 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
enum dpio_channel ch = vlv_dport_to_channel(dport);
int pipe = intel_crtc->pipe;
int data, i;
+ u32 val;
- /* Program Tx lane latency optimal setting*/
mutex_lock(&dev_priv->dpio_lock);
+
+ /* Deassert soft data lane reset*/
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+ val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+
+ /* Program Tx lane latency optimal setting*/
for (i = 0; i < 4; i++) {
/* Set the latency optimal bit */
data = (i == 1) ? 0x0 : 0x6;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 4f8deba..fbba669 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1214,8 +1214,14 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
int data, i;
u32 val;
- /* Program Tx latency optimal setting */
mutex_lock(&dev_priv->dpio_lock);
+
+ /* Deassert soft data lane reset*/
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+ val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+
+ /* Program Tx latency optimal setting */
for (i = 0; i < 4; i++) {
/* Set the latency optimal bit */
data = (i == 1) ? 0x0 : 0x6;
--
1.8.3.2
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