This adds the required helpers for saving/restoring HW context when
going to D3 (and possibly to S0ix afterwards) state on VLV and then
enables RPM.
Since we depend on the RC6 power context mechanism to save some state
this also touches generic RPM parts, so that RPM is only enabled after
the delayed RC6 enabling completes.
For more details on the VLV specific parts see patches 13 and 14.
I also included a related bugfix that Daniel and Paulo were also looking
at (patch 7).
I tested this with igt/kms_flip and pm_pc8 on VLV/DP, they seem to pass
fine, although I'm not sure that pm_pc8 goes through all interesting
paths, I'm planning to check this next.
Imre Deak (15):
drm/i915: vlv: clean up GTLC wake control/status register macros
drm/i915: vlv: clear master interrupt flag when disabling interrupts
drm/i915: vlv: add RC6 residency counters
drm/i915: fix rc6 status debug print
drm/i915: take init power domain for sysfs/debugfs entries where
needed
drm/i915: get init power domain for gpu error state capture
drm/i915: vlv: check port power domain instead of only D0 for eDP VDD
on
drm/i915: vlv: setup RPS min/max frequencies once during init time
drm/i915: vlv: factor out vlv_force_gfx_clock
drm/i915: disable runtime PM until delayed RPS/RC6 enabling completes
drm/i915: vlv: disable RPM if RC6 is not enabled
drm/i915: add various missing GTI/Gunit register definitions
drm/i915: vlv: add gunit s0ix save/restore helpers
drm/i915: vlv: add runtime PM support
drm/i915: vlv: enable RPM
drivers/gpu/drm/i915/i915_debugfs.c | 22 +-
drivers/gpu/drm/i915/i915_drv.c | 399 +++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_drv.h | 65 +++++-
drivers/gpu/drm/i915/i915_gem.c | 5 +-
drivers/gpu/drm/i915/i915_irq.c | 6 +
drivers/gpu/drm/i915/i915_reg.h | 56 ++++-
drivers/gpu/drm/i915/i915_sysfs.c | 4 +
drivers/gpu/drm/i915/intel_dp.c | 6 +-
drivers/gpu/drm/i915/intel_drv.h | 3 +
drivers/gpu/drm/i915/intel_pm.c | 136 ++++++++----
10 files changed, 647 insertions(+), 55 deletions(-)
--
1.8.4
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