The spec changed the order awhile back to put the ports at the end
again, but we never updated. Things seem to work ok either way, but
apparently there are some failures fixed by the new order, so let's just
go ahead and do it.
Signed-off-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index df7cc11..98cf24f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1842,7 +1842,23 @@ static void g4x_enable_dp(struct intel_encoder *encoder)
static void vlv_enable_dp(struct intel_encoder *encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+ struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ uint32_t dp_reg = I915_READ(intel_dp->output_reg);
+
+ if (WARN_ON(dp_reg & DP_PORT_EN))
+ return;
+ intel_edp_panel_vdd_on(intel_dp);
+ intel_dp_start_link_train(intel_dp);
+ if (!is_edp(intel_dp))
+ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+ intel_edp_panel_on(intel_dp);
+ vlv_wait_port_ready(dev_priv, dport);
+ edp_panel_vdd_off(intel_dp, true);
+ intel_dp_complete_link_train(intel_dp);
+ intel_dp_stop_link_train(intel_dp);
intel_edp_backlight_on(intel_dp);
}
@@ -1888,10 +1904,6 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
&power_seq);
}
-
- intel_enable_dp(encoder);
-
- vlv_wait_port_ready(dev_priv, dport);
}
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
--
1.8.4.2
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