On Thu, 03 Apr 2014, Vandana Kannan <vandana.kannan@xxxxxxxxx> wrote:
> From: Pradeep Bhat <pradeep.bhat@xxxxxxxxx>
>
> This patch and finds out the lowest refresh rate supported for the resolution
> same as the fixed_mode.
> It also checks the VBT fields to see if panel supports seamless DRRS or not.
> Based on above data it marks whether eDP panel supports seamless DRRS or not.
> This information is needed for supporting seamless DRRS switch for certain
> power saving usecases. This patch is tested by enabling the DRM logs and
> user should see whether Seamless DRRS is supported or not.
>
> v2: Daniel's review comments
> Modified downclock deduction based on intel_find_panel_downclock
>
> v3: Chris's review comments
> Moved edp_downclock_avail and edp_downclock to intel_panel
>
> v4: Jani's review comments.
> Changed name of the enum edp_panel_type to drrs_support type.
> Change is_drrs_supported to drrs_support of type enum drrs_support_type.
>
> v5: Incorporated Jani's review comments
> Modify intel_dp_drrs_initialize to return downclock mode. Support for Gen7
> and above.
>
> v6: Incorporated Chris's review comments.
> Changed initialize to init in intel_drrs_initialize
>
> v7: Incorporated Jani's review comments.
> Removed edp_downclock and edp_downclock_avail. Return NULL explicitly.
> Make drrs_state and unnamed struct. Move Gen based check inside drrs_init.
>
> v8: Made changes to track PSR enable/disable throughout system use (instead
> of just in the init sequence) for disabling/enabling DRRS. Jani's review
> comments.
>
> Signed-off-by: Pradeep Bhat <pradeep.bhat@xxxxxxxxx>
> Signed-off-by: Vandana Kannan <vandana.kannan@xxxxxxxxx>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 ++++
> drivers/gpu/drm/i915/intel_dp.c | 55 +++++++++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_drv.h | 16 ++++++++++++
> 3 files changed, 75 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cd73a33..b6ea225 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -794,6 +794,10 @@ struct i915_fbc {
> } no_fbc_reason;
> };
>
> +struct i915_drrs {
> + bool is_psr_enabled;
> +};
> +
> struct i915_psr {
> bool sink_support;
> bool source_ok;
> @@ -1497,6 +1501,7 @@ typedef struct drm_i915_private {
> struct timer_list hotplug_reenable_timer;
>
> struct i915_fbc fbc;
> + struct i915_drrs drrs;
> struct intel_opregion opregion;
> struct intel_vbt_data vbt;
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 59ee4dc..ce588d1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1697,6 +1697,7 @@ static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
> static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + struct drm_i915_private *dev_priv = dev->dev_private;
>
> if (!intel_edp_psr_match_conditions(intel_dp) ||
> intel_edp_is_psr_enabled(dev))
> @@ -1710,6 +1711,11 @@ static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
>
> /* Enable PSR on the host */
> intel_edp_psr_enable_source(intel_dp);
> +
> + if (INTEL_INFO(dev)->gen < 8) {
> + dev_priv->drrs.is_psr_enabled = true;
> + DRM_DEBUG_KMS("eDP panel PSR enabled. Can't support DRRS\n");
> + }
I'm quite certain we have adequate tracking for whether psr is enabled
or not. Do not add more state for the same thing.
Whenever you'd need to check for dev_priv->drrs.is_psr_enabled, you can
dig it out from existing psr functions.
My whole point was you should not do this at initialization time:
if (psr enabled at this arbitrary point during init)
can't use drrs until reboot or driver reloaded
BR,
Jani.
> }
>
> void intel_edp_psr_enable(struct intel_dp *intel_dp)
> @@ -1736,6 +1742,9 @@ void intel_edp_psr_disable(struct intel_dp *intel_dp)
> if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
> EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
> DRM_ERROR("Timed out waiting for PSR Idle State\n");
> +
> + if (INTEL_INFO(dev)->gen < 8)
> + dev_priv->drrs.is_psr_enabled = false;
> }
>
> void intel_edp_psr_update(struct drm_device *dev)
> @@ -3611,6 +3620,44 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> I915_READ(pp_div_reg));
> }
>
> +static struct drm_display_mode *
> +intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
> + struct intel_connector *intel_connector,
> + struct drm_display_mode *fixed_mode)
> +{
> + struct drm_connector *connector = &intel_connector->base;
> + struct intel_dp *intel_dp = &intel_dig_port->dp;
> + struct drm_device *dev = intel_dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_display_mode *downclock_mode = NULL;
> +
> + if (INTEL_INFO(dev)->gen <= 6) {
> + DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
> + return NULL;
> + }
> +
> + if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev))
> + dev_priv->drrs.is_psr_enabled = true;
> +
> + if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) {
> + DRM_INFO("VBT doesn't support DRRS\n");
> + return NULL;
> + }
> +
> + downclock_mode = intel_find_panel_downclock
> + (dev, fixed_mode, connector);
> +
> + if (downclock_mode != NULL &&
> + dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) {
> + intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
> +
> + intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
> + DRM_INFO("seamless DRRS supported for eDP panel.\n");
> + }
> +
> + return downclock_mode;
> +}
> +
> static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> struct intel_connector *intel_connector,
> struct edp_power_seq *power_seq)
> @@ -3620,10 +3667,13 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> struct drm_device *dev = intel_dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct drm_display_mode *fixed_mode = NULL;
> + struct drm_display_mode *downclock_mode = NULL;
> bool has_dpcd;
> struct drm_display_mode *scan;
> struct edid *edid;
>
> + intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
> +
> if (!is_edp(intel_dp))
> return true;
>
> @@ -3665,6 +3715,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> list_for_each_entry(scan, &connector->probed_modes, head) {
> if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
> fixed_mode = drm_mode_duplicate(dev, scan);
> + downclock_mode = intel_dp_drrs_init(
> + intel_dig_port,
> + intel_connector, fixed_mode);
> break;
> }
> }
> @@ -3677,7 +3730,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
> }
>
> - intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
> + intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
> intel_panel_setup_backlight(connector);
>
> return true;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index fa99104..d781165 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -483,6 +483,17 @@ struct intel_hdmi {
>
> #define DP_MAX_DOWNSTREAM_PORTS 0x10
>
> +/**
> + * HIGH_RR is the highest eDP panel refresh rate read from EDID
> + * LOW_RR is the lowest eDP panel refresh rate found from EDID
> + * parsing for same resolution.
> + */
> +enum edp_drrs_refresh_rate_type {
> + DRRS_HIGH_RR,
> + DRRS_LOW_RR,
> + DRRS_MAX_RR, /* RR count */
> +};
> +
> struct intel_dp {
> uint32_t output_reg;
> uint32_t aux_ch_ctl_reg;
> @@ -521,6 +532,11 @@ struct intel_dp {
> bool has_aux_irq,
> int send_bytes,
> uint32_t aux_clock_divider);
> + struct {
> + enum drrs_support_type type;
> + enum edp_drrs_refresh_rate_type refresh_rate_type;
> + } drrs_state;
> +
> };
>
> struct intel_digital_port {
> --
> 1.9.1
>
--
Jani Nikula, Intel Open Source Technology Center
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