On Wed, Apr 02, 2014 at 07:46:37PM -0700, Ben Widawsky wrote: > It seems we need this at least for the current platforms we have, but > probably not later. In any event, it should cause too much harm as we do > the same thing on several other platforms. > > Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index fa00185..f73f8ca 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4868,6 +4868,10 @@ static void gen8_init_clock_gating(struct drm_device *dev) > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); > > + /* WaDisableDopClockGating:bdw May not be needed for production */ > + I915_WRITE(GEN7_ROW_CHICKEN2, > + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); The hsd says you should also disable tcunit clock gating in GEN6_UCGCTL1. There's another w/a by the name of WaDisableRowChickenDopClockGating which seems to be the same thing (apart from the tcunit bit maybe). You might want to add that w/a note as well. > + > /* WaSwitchSolVfFArbitrationPriority:bdw */ > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); > > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
