On Wed, Apr 02, 2014 at 10:08:54AM -0700, Jesse Barnes wrote: > Needs to happen after clock is running or it doesn't behave correctly. Subject of the patch isn't correct. You enable it after the PLL, but still before the port gets enabled. Which I believe is the order we want. So you should just fix the patch subject. Apart from that I think it should work out just fine: Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> BTW now that we do this, we should also disable the DIP after disabling the port. Otherwise when we move a pipe from a HDMI port to some other type of port we leave the DIP enabled and might continue sending infoframes to some unsuspecting sink. That bug has been present since forever, but now it could actually be fixed. > > Signed-off-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_hdmi.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > index fb9839b..a4ca63b6 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -669,8 +669,6 @@ static void intel_hdmi_mode_set(struct intel_encoder *encoder) > > I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); > POSTING_READ(intel_hdmi->hdmi_reg); > - > - intel_hdmi->set_infoframes(&encoder->base, adjusted_mode); > } > > static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, > @@ -738,9 +736,13 @@ static void intel_enable_hdmi(struct intel_encoder *encoder) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); > struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); > + struct drm_display_mode *adjusted_mode = > + &intel_crtc->config.adjusted_mode; > u32 temp; > u32 enable_bits = SDVO_ENABLE; > > + intel_hdmi->set_infoframes(&encoder->base, adjusted_mode); > + > if (intel_hdmi->has_audio) > enable_bits |= SDVO_AUDIO_ENABLE; > > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
