On Mon, Mar 31, 2014 at 06:21:27PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > DPIO reads from groups/broadcast register offsets for PCS and > TX return all 1's. If that result gets used for something > we'll probably end up doing something wrong. So warn when that > happens. > > FIXME there might be some registers where all 1's is a valid value, > so ideally we should check the register offset instead... FIXMEs like this look better in the code, I've pasted it there, too. -Daniel > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_sideband.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c > index 0954f13..c1e56f5 100644 > --- a/drivers/gpu/drm/i915/intel_sideband.c > +++ b/drivers/gpu/drm/i915/intel_sideband.c > @@ -182,6 +182,10 @@ u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) > > vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)), > DPIO_OPCODE_REG_READ, reg, &val); > + > + WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n", > + pipe_name(pipe), reg, val); > + > return val; > } > > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
