On Tue, Apr 01, 2014 at 07:39:47PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> > > Because if we keep the current code, we'll get tons of WARNs on > Broadwell, since the code is Haswell-specific. > > We could have also added a Broadwell-specific code there, but it's not > really needed since we never disable LCPLL with the hotplug interrupts > still enabled. So keep the easy-and-simple-to-maintain solution until > we actually need something else. > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> I'll see how quickly QA reports this before merging it. If you spot the bug please reply with the Bugzilla: tag, thanks. -Daniel > --- > drivers/gpu/drm/i915/intel_display.c | 17 +++++++---------- > 1 file changed, 7 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 3fb3bd3..6691970 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6861,8 +6861,6 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) > struct drm_device *dev = dev_priv->dev; > struct intel_ddi_plls *plls = &dev_priv->ddi_plls; > struct intel_crtc *crtc; > - unsigned long irqflags; > - uint32_t val; > > list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) > WARN(crtc->active, "CRTC for pipe %c enabled\n", > @@ -6883,14 +6881,13 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) > "Utility pin enabled\n"); > WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); > > - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); > - val = I915_READ(DEIMR); > - WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff, > - "Unexpected DEIMR bits enabled: 0x%x\n", val); > - val = I915_READ(SDEIMR); > - WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, > - "Unexpected SDEIMR bits enabled: 0x%x\n", val); > - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); > + /* > + * In theory we can still leave IRQs enabled, as long as only the HPD > + * interrupts remain enabled. We used to check for that, but since it's > + * gen-specific and since we only disable LCPLL after we fully disable > + * the interrupts, the check below should be enough. > + */ > + WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n"); > } > > static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) > -- > 1.8.5.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
