On Tue, Apr 01, 2014 at 12:18:24PM -0700, Ben Widawsky wrote: > On Tue, Apr 01, 2014 at 02:51:27PM +0100, Damien Lespiau wrote: > > On Tue, Apr 01, 2014 at 02:47:19PM +0100, Mateo Lozano, Oscar wrote: > > > > > --- a/drivers/gpu/drm/i915/i915_lrc.c > > > > > +++ b/drivers/gpu/drm/i915/i915_lrc.c > > > > > @@ -41,7 +41,45 @@ > > > > > #include <drm/i915_drm.h> > > > > > #include "i915_drv.h" > > > > > > > > > > +#define GEN8_LR_CONTEXT_SIZE (21 * PAGE_SIZE) > > > > > > > > I'm a bit puzzled by that number: > > > > - I found a sentence saying: "the Context Image for the rendering > > > > engine consists of 20 4K pages", which seems that it includes the > > > > HWS page (on the same page it says context layout = HWS Page + > > > > register state context). > > > > - When looking at the register state context for the render engine: > > > > 18096 dwords -> 18 pages, so in total it'd be 19 pages (need to add > > > > the HWS Page) > > > > - Clearly I must be missing something :) > > > > - That's only for the render engine, other engines have a much smaller > > > > context, smaller enough that it's worth looking at their exact size. > > > > - It'd be nice to work out the real size from the *CXT_*SIZE > > > > registers. > > > > > > Hmmmm... I´ll try to get the real context sizes from the registers and > > > compare. At least for RCS, VCS and BCS since there doesn´t seem to be > > > a register for VECS? > > > > Couldn't find it either. I guess we'll need to ask the help of a friend. > > Or the 50/50 joker maybe. > > > > -- > > Damien > > CXT_SIZE is total garbage on anything past Ivybridge. That's why we > don't use it for HSW either... I know, right? We should request the spec > get updated. I have no excuse for not requesting that sooner. (talking about BDW only) For the render ring: HWSP: 4KB Ring context: CTX_SIZE[26:24] 5 cache lines -> offsets (in DW) 0x0 to 0x4f (= 5 * 64 / 4) Render context: CTX_SIZE[23:16] -> 0x65 caches lines -> offets (in DW) 0x50 to 0x69f (= 0x50 + 0x65 * 64 / 4 - 1) VF/VFE context CTX_SIZE[7:0] -> 0x82 cache lines -> offsets (in DW) 0x6A0 to 0xebf (= 0x6a0 + 0x82*64/4 - 1) Atomic storage is the max that you can allocate, 32KB ie 8192 DWords So we're almost there. What's missing here is the RS context size, couldn't find it in the spec :/ Maybe because that is a "well known" value. Note that I don't actually know what we read back from hw. Considering that the BCS context size seems to be 2 pages, I think it's worth digging a bit more to save ~66KB per BCS context (for instance). Even if we have to hardcode the different context sizes. -- Damien _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
