From: Ben Widawsky <benjamin.widawsky@xxxxxxxxx> Logical ring contexts do not need most of the ring init: we just need the pipe control object for the render ring and a few other things (some of which will be added later). Signed-off-by: Oscar Mateo <oscar.mateo@xxxxxxxxx> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 42 ++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index a18dcf7..6e53ce1 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -528,6 +528,18 @@ out: return ret; } +static int init_ring_common_lrc(struct intel_engine *ring) +{ + struct intel_ringbuffer *ringbuf = __get_ringbuf(ring); + + ringbuf->head = 0; + ringbuf->tail = 0; + ringbuf->space = ringbuf->size; + ringbuf->last_retired_head = -1; + + return 0; +} + static int init_pipe_control(struct intel_engine *ring) { @@ -630,6 +642,12 @@ static int init_render_ring(struct intel_engine *ring) return ret; } +static int init_render_ring_lrc(struct intel_engine *ring) +{ + init_ring_common_lrc(ring); + return init_pipe_control(ring); +} + static void render_ring_cleanup(struct intel_engine *ring) { struct drm_device *dev = ring->dev; @@ -1914,14 +1932,17 @@ int intel_init_render_ring(struct drm_device *dev) struct intel_engine *ring = &dev_priv->ring[RCS]; ring->write_tail = ring_write_tail; + ring->init = init_render_ring; if (INTEL_INFO(dev)->gen >= 6) { ring->add_request = gen6_add_request; ring->flush = gen7_render_ring_flush; if (INTEL_INFO(dev)->gen == 6) ring->flush = gen6_render_ring_flush; if (INTEL_INFO(dev)->gen >= 8) { - if (dev_priv->lrc_enabled) + if (dev_priv->lrc_enabled) { ring->write_tail = gen8_write_tail_lrc; + ring->init = init_render_ring_lrc; + } ring->flush = gen8_render_ring_flush; ring->irq_get = gen8_ring_get_irq; ring->irq_put = gen8_ring_put_irq; @@ -1980,7 +2001,6 @@ int intel_init_render_ring(struct drm_device *dev) ring->dispatch_execbuffer = i830_dispatch_execbuffer; else ring->dispatch_execbuffer = i915_dispatch_execbuffer; - ring->init = init_render_ring; ring->cleanup = render_ring_cleanup; /* Workaround batchbuffer to combat CS tlb bug. */ @@ -2079,6 +2099,7 @@ int intel_init_bsd_ring(struct drm_device *dev) struct intel_engine *ring = &dev_priv->ring[VCS]; ring->write_tail = ring_write_tail; + ring->init = init_ring_common; if (INTEL_INFO(dev)->gen >= 6) { /* gen6 bsd needs a special wa for tail updates */ if (IS_GEN6(dev)) @@ -2088,8 +2109,10 @@ int intel_init_bsd_ring(struct drm_device *dev) ring->get_seqno = gen6_ring_get_seqno; ring->set_seqno = ring_set_seqno; if (INTEL_INFO(dev)->gen >= 8) { - if (dev_priv->lrc_enabled) + if (dev_priv->lrc_enabled) { ring->write_tail = gen8_write_tail_lrc; + ring->init = init_ring_common_lrc; + } ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; ring->irq_get = gen8_ring_get_irq; @@ -2128,7 +2151,6 @@ int intel_init_bsd_ring(struct drm_device *dev) } ring->dispatch_execbuffer = i965_dispatch_execbuffer; } - ring->init = init_ring_common; return intel_init_ring(dev, ring); } @@ -2139,13 +2161,16 @@ int intel_init_blt_ring(struct drm_device *dev) struct intel_engine *ring = &dev_priv->ring[BCS]; ring->write_tail = ring_write_tail; + ring->init = init_ring_common; ring->flush = gen6_ring_flush; ring->add_request = gen6_add_request; ring->get_seqno = gen6_ring_get_seqno; ring->set_seqno = ring_set_seqno; if (INTEL_INFO(dev)->gen >= 8) { - if (dev_priv->lrc_enabled) + if (dev_priv->lrc_enabled) { ring->write_tail = gen8_write_tail_lrc; + ring->init = init_ring_common_lrc; + } ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; ring->irq_get = gen8_ring_get_irq; @@ -2166,7 +2191,6 @@ int intel_init_blt_ring(struct drm_device *dev) ring->signal_mbox[VCS] = GEN6_VBSYNC; ring->signal_mbox[BCS] = GEN6_NOSYNC; ring->signal_mbox[VECS] = GEN6_VEBSYNC; - ring->init = init_ring_common; return intel_init_ring(dev, ring); } @@ -2177,14 +2201,17 @@ int intel_init_vebox_ring(struct drm_device *dev) struct intel_engine *ring = &dev_priv->ring[VECS]; ring->write_tail = ring_write_tail; + ring->init = init_ring_common; ring->flush = gen6_ring_flush; ring->add_request = gen6_add_request; ring->get_seqno = gen6_ring_get_seqno; ring->set_seqno = ring_set_seqno; if (INTEL_INFO(dev)->gen >= 8) { - if (dev_priv->lrc_enabled) + if (dev_priv->lrc_enabled) { ring->write_tail = gen8_write_tail_lrc; + ring->init = init_ring_common_lrc; + } ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; ring->irq_get = gen8_ring_get_irq; @@ -2205,7 +2232,6 @@ int intel_init_vebox_ring(struct drm_device *dev) ring->signal_mbox[VCS] = GEN6_VVESYNC; ring->signal_mbox[BCS] = GEN6_BVESYNC; ring->signal_mbox[VECS] = GEN6_NOSYNC; - ring->init = init_ring_common; return intel_init_ring(dev, ring); } -- 1.9.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx