On Fri, Mar 21, 2014 at 06:02:36PM +0530, sourab.gupta@xxxxxxxxx wrote: > From: Akash Goel <akash.goel@xxxxxxxxx> > > Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'. > In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI > Store data commands. > > v2: Modified the WA comment (Ville) > > v3: Added the vlv identifier with WA name (Damien) > > Signed-off-by: Akash Goel <akash.goel@xxxxxxxxx> > Signed-off-by: Sourab Gupta <sourab.gupta@xxxxxxxxx> We seem to have a bit a mess of vlv w/a patches with them splattered over multiple threads and the discussion split up equally badly. And I'm no longer clear at all which patches are superseeded and where exactly I can find the latest version of each. Can you please dig up all the vlv w/a patches you have in-flight and resubmit them in a new thread? Also when resubmitting individual patches of a series you need to set the in-reply-to for each individual patch to it's previous version, otherwise it's really hard to follow. Top-posting and lumping a few resends together just confuses things. And if a thread gets too messy the best option is always to start a new clean thread. -Daniel > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 4eb3e06..2cc7ed5 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -2207,6 +2207,28 @@ intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) > uint32_t flush_domains; > int ret; > > + if (IS_VALLEYVIEW(ring->dev)) { > + /* > + * WaTlbInvalidateStoreDataBefore:vlv > + * Before pipecontrol with TLB invalidate set, need 2 store > + * data commands (such as MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) > + * Without this, hardware cannot guarantee the command after the > + * PIPE_CONTROL with TLB inv will not use the old TLB values. > + */ > + int i; > + ret = intel_ring_begin(ring, 4 * 2); > + if (ret) > + return ret; > + for (i = 0; i < 2; i++) { > + intel_ring_emit(ring, MI_STORE_DWORD_INDEX); > + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX << > + MI_STORE_DWORD_INDEX_SHIFT); > + intel_ring_emit(ring, 0); > + intel_ring_emit(ring, MI_NOOP); > + } > + intel_ring_advance(ring); > + } > + > flush_domains = 0; > if (ring->gpu_caches_dirty) > flush_domains = I915_GEM_GPU_DOMAINS; > -- > 1.8.5.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx