On Fri, Mar 21, 2014 at 01:16:43PM +0000, Chris Wilson wrote: > It is important that the user is fully aware that the seemingly atomic > read/write of a 64-bit value from MMIO space, may in fact be 2 separate > reads of 32-bits. This can lead to hilarity, such as s/reads/operations/ > > commit d18b9619034230b6f945e215276425636ca401fe > Author: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Date: Wed Jul 10 13:36:23 2013 +0100 > > drm/i915: Fix incoherence with fence updates on Sandybridge+ > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> Indeed, there's no stern enough warning for this! Queued for -next, thanks for the patch. -Daniel > --- > drivers/gpu/drm/i915/i915_drv.h | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 4c09fb2ff1b5..a7a3e9ed10d4 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2783,6 +2783,12 @@ void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); > #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) > #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) > > +/* Be very careful with read/write 64-bit values. On 32-bit machines, they > + * will be implemented using 2 32-bit writes in an arbitrary order with > + * an arbitrary delay between them. This can cause the hardware to > + * act upon the intermediate value, possibly leading to corruption and > + * machine death. You have been warned. > + */ > #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) > #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) > > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
