On Mon, Mar 17, 2014 at 01:17:32PM +0000, Chris Wilson wrote: > On Sat, Mar 15, 2014 at 11:30:18AM -0700, Ben Widawsky wrote: > > On Sat, Mar 15, 2014 at 03:20:23PM +0000, Chris Wilson wrote: > > > On Sat, Mar 15, 2014 at 12:47:22PM +0100, Daniel Vetter wrote: > > > > On Fri, Mar 14, 2014 at 05:21:36PM -0700, Ben Widawsky wrote: > > > > > Broken by: > > > > > commit 0294ae7b44bba7ab0d4cef9a8736287f38bdb4fd > > > > > Author: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > > > > Date: Thu Mar 13 12:00:29 2014 +0000 > > > > > > > > > > drm/i915: Consolidate forcewake resetting to a single function > > > > > > > > > > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > > > > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> > > > > > Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx> > > > > > --- > > > > > drivers/gpu/drm/i915/intel_uncore.c | 6 +++--- > > > > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > > > > > index e6bb421..7e55ceb 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > > > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > > > > @@ -362,6 +362,9 @@ void intel_uncore_early_sanitize(struct drm_device *dev) > > > > > { > > > > > struct drm_i915_private *dev_priv = dev->dev_private; > > > > > > > > > > + setup_timer(&dev_priv->uncore.force_wake_timer, > > > > > + gen6_force_wake_timer, (unsigned long)dev_priv); > > > > > > > > We call early_sanitize also from our resume code, so this will now > > > > re-setup the timer again. We generally don't do that since if we ever leak > > > > the timer to here in an enabled state it causes havoc. > > > > > > Gah, really? intel_uncore_early_init()! There must be a clean way to > > > break this up. > > > -Chris > > > > At least in the code base I was looking at, we currently do this also, > > so I didn't think this was any worse. > > > > With lockdep turned on, the module will not even load, so please either > > revert the original, or merge this. > > I think we can just: > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index a62ff21..c9fcc20 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -317,9 +317,10 @@ static void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) > { > struct drm_i915_private *dev_priv = dev->dev_private; > unsigned long irqflags; > - int pending; > + int pending = 0; > > - pending = del_timer_sync(&dev_priv->uncore.force_wake_timer); > + if (dev_priv->uncore.force_wake_timer.function) > + pending = del_timer_sync(&dev_priv->uncore.force_wake_timer); > > /* Hold uncore.lock across reset to prevent any register access > * with forcewake not set correctly > > i.e. > > - del_timer_sync(&dev_priv->uncore.force_wake_timer); > + if (dev_priv->uncore.force_wake_timer.function) > + del_timer_sync(&dev_priv->uncore.force_wake_timer); I've thought of this: diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index e4d2b9f15ae2..9faee49f210d 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1608,8 +1608,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) goto put_bridge; } - intel_uncore_early_sanitize(dev); - /* This must be called before any calls to HAS_PCH_* */ intel_detect_pch(dev); diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index e2e328d86aff..c3832d9270a6 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -736,6 +736,8 @@ void intel_uncore_init(struct drm_device *dev) setup_timer(&dev_priv->uncore.force_wake_timer, gen6_force_wake_timer, (unsigned long)dev_priv); + intel_uncore_early_sanitize(dev); + if (IS_VALLEYVIEW(dev)) { dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx