On Sat, Mar 15, 2014 at 12:08:56AM +0100, Daniel Vetter wrote:
> Currently not an issue since we don't emit sempahores, but better
> not forget about those.
>
> As a little prep work extract the ipehr decoding for cleaner control
> flow. And apply a bit of polish.
>
> Cc: Ben Widawsky <ben@xxxxxxxxxxxx>
> Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
Reviewed-by: Ben Widawsky <ben@xxxxxxxxxxxx>
I've made a note to add the relevant BDW patch already.
one comment below.
> ---
> drivers/gpu/drm/i915/i915_irq.c | 20 ++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> 2 files changed, 20 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 473372a6c97d..0f3a6d791502 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2525,6 +2525,23 @@ ring_idle(struct intel_ring_buffer *ring, u32 seqno)
> i915_seqno_passed(seqno, ring_last_seqno(ring)));
> }
>
> +static bool
> +ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
> +{
> + if (INTEL_INFO(dev)->gen >= 8) {
> + /*
> + * FIXME: gen8 semaphore support - currently we don't emit
> + * semaphores on bdw anyway, but this needs to be addressed when
> + * we merge that code.
> + */
> + return false;
> + } else {
If you wanted to be paranoid:
WARN_ON((ipehr & MI_SEMAPHORE_SYNC_MASK) == MI_SEMAPHORE_SYNC_INVALID)
> + ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
> + return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
> + MI_SEMAPHORE_REGISTER);
> + }
> +}
> +
> static struct intel_ring_buffer *
> semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
> {
> @@ -2533,8 +2550,7 @@ semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
> int i;
>
> ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
> - if ((ipehr & ~(0x3 << 16)) !=
> - (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
> + if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
> return NULL;
>
> /*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 146609ab42bb..23267859156f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -244,7 +244,8 @@
> #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
> #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
> #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
> -#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
> +#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
> +#define MI_SEMAPHORE_SYNC_MASK (3<<16)
> #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
> #define MI_MM_SPACE_GTT (1<<8)
> #define MI_MM_SPACE_PHYSICAL (0<<8)
> --
> 1.8.1.4
>
--
Ben Widawsky, Intel Open Source Technology Center
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