On Wed, Mar 12, 2014 at 07:21:45PM -0700, Ben Widawsky wrote: > I'm missing something on the original patch, > 884020bf3d2a3787a1cc6df902e98e0eec60330b. How were we emitting > breadcrumbs without flushing the TLB? All bathcbuffers should be > bookended by a TLB invalidate already, so I'm not sure the logic holds. > Chris could explain that one a bit further? Upon resume, the hardware continues writing the breadcrumbs into the old hws page (due to the stale TLB) and we try to read the seqno from the new page, so as shown by the error-states it appears that the breadcrumb writes are not happening. Since the hardware is writing to a random address, we are now corrupting random memory. Which is what I thought I said in the changelog. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
