On Tue, 4 Mar 2014 19:23:09 +0200 Imre Deak <imre.deak@xxxxxxxxx> wrote: > Needed by the next patch, wanting to set the underrun reporting as part > of a bigger dev_priv->irq_lock'ed sequence. > > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_irq.c | 20 +++++++++++++++----- > 1 file changed, 15 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 9d9309c..bc94cfb 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -387,17 +387,14 @@ static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, > * > * Returns the previous state of underrun reporting. > */ > -bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, > - enum pipe pipe, bool enable) > +bool intel_set_cpu_fifo_underrun_reporting_nolock(struct drm_device *dev, > + enum pipe pipe, bool enable) > { > struct drm_i915_private *dev_priv = dev->dev_private; > struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > - unsigned long flags; > bool ret; > > - spin_lock_irqsave(&dev_priv->irq_lock, flags); > - > ret = !intel_crtc->cpu_fifo_underrun_disabled; > > if (enable == ret) > @@ -415,7 +412,20 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, > broadwell_set_fifo_underrun_reporting(dev, pipe, enable); > > done: > + return ret; > +} > + > +bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, > + enum pipe pipe, bool enable) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + unsigned long flags; > + bool ret; > + > + spin_lock_irqsave(&dev_priv->irq_lock, flags); > + ret = intel_set_cpu_fifo_underrun_reporting_nolock(dev, pipe, enable); > spin_unlock_irqrestore(&dev_priv->irq_lock, flags); > + > return ret; > } > Funky how diff left the spin_unlock line alone. :) Reviewed-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx