From: Naresh Kumar Kachhi <naresh.kumar.kachhi@xxxxxxxxx>
Based on Bspec the command parser must be stopped prior to
issuing sync flush. Only after observing Rings Idle set in
MI_MODE can a Sync Flush be issued. Once sync flush has
finished the command parser is re-enabled by clearing Stop Rings.
Signed-off-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +++++++++++++
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +++++
3 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f564ce..97d872a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -720,6 +720,7 @@
#define RING_INSTPS(base) ((base)+0x70)
#define RING_DMA_FADD(base) ((base)+0x78)
#define RING_INSTPM(base) ((base)+0xc0)
+#define RING_MI_MODE(base) ((base)+0x9c)
#define INSTPS 0x02070 /* 965+ only */
#define INSTDONE1 0x0207c /* 965+ only */
#define ACTHD_I965 0x02074
@@ -796,6 +797,8 @@
# define VS_TIMER_DISPATCH (1 << 6)
# define MI_FLUSH_ENABLE (1 << 12)
# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
+# define MODE_STOP (1 << 8)
+# define MODE_IDLE (1 << 9)
#define GEN6_GT_MODE 0x20d0
#define GEN6_GT_MODE_HI (1 << 9)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b340c75..477b5dc 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -982,6 +982,15 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
/* Flush the TLB for this page */
if (INTEL_INFO(dev)->gen >= 6) {
u32 reg = RING_INSTPM(ring->mmio_base);
+
+ /* before issuing a sync flush request the ring to go idle */
+ I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(MODE_STOP));
+
+ /* Wait for idle */
+ if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000))
+ /* don't fail here, try to invalidate TLB */
+ DRM_ERROR("%s :timed out trying to stop ring", ring->name);
+
I915_WRITE(reg,
_MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
INSTPM_SYNC_FLUSH));
@@ -989,6 +998,10 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
1000))
DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
ring->name);
+
+ /* Clear the MI_MODE stop bit */
+ I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(MODE_STOP));
+ reg = I915_READ_MODE(ring); /* Barrier read */
}
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 08b91c6..1bb4a01 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -33,6 +33,11 @@ struct intel_hw_status_page {
#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
+#define I915_READ_MODE(ring) \
+ I915_READ(RING_MI_MODE((ring)->mmio_base))
+#define I915_WRITE_MODE(ring, val) \
+ I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
+
enum intel_ring_hangcheck_action {
HANGCHECK_IDLE = 0,
HANGCHECK_WAIT,
--
1.8.1.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
