Baytrail supports per-pipe PSR configuration, however PSR on
PIPE_B isn't working properly. So let's keep it disabled for now.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_dp.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index aabab25..3adc127 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1852,6 +1852,13 @@ static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
return false;
}
+ /* Baytrail supports per-pipe PSR configuration, however PSR on
+ * PIPE_B isn't working properly. So let's keep it disabled for now. */
+ if (IS_VALLEYVIEW(dev) && intel_crtc->pipe != PIPE_A) {
+ DRM_DEBUG_KMS("PSR on BYT isn't enabled on pipe B.\n");
+ return false;
+ }
+
dev_priv->psr.source_ok = true;
return true;
}
--
1.8.3.1
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