Ben Widawsky <benjamin.widawsky@xxxxxxxxx> writes: > On Tue, Feb 18, 2014 at 07:10:24PM +0200, Mika Kuoppala wrote: >> Sometimes generic driver code gets forcewake explicitly by >> gen6_gt_force_wake_get(), which check forcewake_count before accessing >> hardware. However the register access with gen8_write function access >> low level hw accessors directly, ignoring the forcewake_count. This >> leads to nested forcewake get from hardware, in ring init and possibly >> elsewhere, causing forcewake ack clear errors and/or hangs. >> >> Fix this by checking the forcewake count also in gen8_write >> >> v2: Read side doesn't care about shadowed registers, >> Remove __needs_put funkiness from gen8_write. (Ville) >> Improved commit message. >> >> References: https://bugs.freedesktop.org/show_bug.cgi?id=74007 >> Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> >> Cc: Ben Widawsky <benjamin.widawsky@xxxxxxxxx> >> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >> Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> Double signed-off slipped in it seems. > Thanks for finding this. I'd been meaning to track down the extra "Timed > out" messages. I do wonder how this actually fixes a hang. Do you have > any idea? No clear idea. I just suspect that the two writes into FORCEWAKE_MT without proper put/ack dance in between upsets the gpu. Interestingly with init it hangs like 1 out of 2 times, but after a gpu reset, it hangs always. The spot is always the same: I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); -Mika _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
