On Fri, Feb 07, 2014 at 12:14:47PM -0800, Kenneth Graunke wrote: > On 02/04/2014 11:59 AM, ville.syrjala@xxxxxxxxxxxxxxx wrote: > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > According to Bspec we need to disable SF pipelined attribute fetch > > whenever SF outputs exceed 16 and normal clip mode is used. A quick > > glance at Mesa suggests that these conditions could happen. So let's > > just always set the magic bit. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 3 ++- > > drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++ > > 2 files changed, 10 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 7aa2cf5..0334507 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -790,7 +790,8 @@ > > #define _3D_CHICKEN3 0x02090 > > #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) > > #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) > > -#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) > > +#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ > > +#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ > > > > #define MI_MODE 0x0209c > > # define VS_TIMER_DISPATCH (1 << 6) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index 6a09281..7247084 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -4683,6 +4683,14 @@ static void gen6_init_clock_gating(struct drm_device *dev) > > _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); > > > > /* > > + * Bspec says: > > + * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and > > + * 3DSTATE_SF number of SF output attributes is more than 16." > > + */ > > + I915_WRITE(_3D_CHICKEN3, > > + _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); > > + > > + /* > > * According to the spec the following bits should be > > * set in order to enable memory self-refresh and fbc: > > * The bit21 and bit22 of 0x42000 > > > > I'm almost positive Mesa will hit this case. Nice catch! > > Reviewed-by: Kenneth Graunke <kenneth@xxxxxxxxxxxxx> Queued for -next, thanks for the patch. Any chance that this would apply to one of our leftover snb gpu hang issues? -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
