On Fri, Feb 7, 2014 at 5:17 PM, Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > On Fri, Feb 07, 2014 at 04:09:48PM -0200, Rodrigo Vivi wrote: >> On the current structure HSW doesn't support PSR with sprites enabled >> but sprites can be enabled after PSR was enabled what would cause >> user to miss screen updates. >> >> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> >> --- >> drivers/gpu/drm/i915/intel_sprite.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c >> index 336ae6c..3132686 100644 >> --- a/drivers/gpu/drm/i915/intel_sprite.c >> +++ b/drivers/gpu/drm/i915/intel_sprite.c >> @@ -318,6 +318,8 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, >> I915_WRITE(SPRSURF(pipe), >> i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); >> POSTING_READ(SPRSURF(pipe)); >> + >> + intel_edp_psr_update(dev); > > I was thinking this might be better placed in intel_update_plane() > since the fbc/ips stuff is there, but I can live with it being here too. I agree there is better. > > But should if have a HSW check on it? BDW doesn't have this restriction > anymore, right? yes, it should... you are right! > >> } >> >> static void >> -- >> 1.7.11.7 > > -- > Ville Syrjälä > Intel OTC I also agree with Daniel we need a test case for that... so, will provide this and a new patch version later -- Rodrigo Vivi Blog: http://blog.vivi.eng.br _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
