On Fri, Feb 07, 2014 at 05:52:12PM +0530, akash.goel@xxxxxxxxx wrote:
> From: Akash Goel <akash.goel@xxxxxxxxx>
>
> Modified programming of following 2 regs in Render ring initialisation fn.
> 1. GFX_MODE_GEN7 (Enabling TLB invalidate)
> 2. MI_MODE (Enabling MI Flush)
>
> v2: Removed the enabling of MI_FLUSH (Ville)
> Added new comments (Ville).
>
> Signed-off-by: Akash Goel <akash.goel@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 19 ++++++++++++++-----
> 1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 49370a1..0d7d927b 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -563,7 +563,10 @@ static int init_render_ring(struct intel_ring_buffer *ring)
> int ret = init_ring_common(ring);
>
> if (INTEL_INFO(dev)->gen > 3)
> - I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
> + /* FIXME, should also apply to ivb */
> + if (!IS_VALLEYVIEW(dev))
> + I915_WRITE(MI_MODE,
> + _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
Was this supposed to be here? I guess it should be a separate patch.
>
> /* We need to disable the AsyncFlip performance optimisations in order
> * to use MI_WAIT_FOR_EVENT within the CS. It should already be
> @@ -579,10 +582,16 @@ static int init_render_ring(struct intel_ring_buffer *ring)
> I915_WRITE(GFX_MODE,
> _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
>
> - if (IS_GEN7(dev))
> - I915_WRITE(GFX_MODE_GEN7,
> - _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
> - _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
> + if (IS_GEN7(dev)) {
> + if (IS_VALLEYVIEW(dev)) {
> + /* FIXME, should also apply to ivb */
> + I915_WRITE(GFX_MODE_GEN7,
> + _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
> + } else
> + I915_WRITE(GFX_MODE_GEN7,
> + _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
> + _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
> + }
>
> if (INTEL_INFO(dev)->gen >= 5) {
> ret = init_pipe_control(ring);
> --
> 1.8.5.2
>
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--
Ville Syrjälä
Intel OTC
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