On Thu, Feb 06, 2014 at 10:22:28AM +0000, Goel, Akash wrote: > Please kindly review this patch. > > Best regards > Akash > -----Original Message----- > From: Goel, Akash > Sent: Thursday, January 09, 2014 5:55 PM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: Goel, Akash > Subject: [PATCH] drm/i915/vlv: Added write-enable pte bit support > > From: Akash Goel <akash.goel@xxxxxxxxx> > > This adds support for using the write-enable bit in the GTT entry for VLV. > This is handled via a read-only flag in the GEM buffer object which is then used to check if the write-enable bit has to be set or not when writing the GTT entries. > Currently by default only the Batch buffer & Ring buffers are being marked as read only. Don't cause us to rewrite the PTE for the batch buffer between each execbuffer (ro for the batch, rw next time it gets used as a texture). In fact, do not change ro without user intervention. gt_old_ro is unused Use byt_pte_encode() instead of hacking the result of ppgtt->pte_encode(). Consider expanding i915_cache_level so that it included the concept of PROT_READ | PROT_WRITE. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
