On Wed, Feb 05, 2014 at 07:33:28AM -0800, Jani Nikula wrote:
> On Wed, 29 Jan 2014, bradley.d.volkin@xxxxxxxxx wrote:
> > From: Brad Volkin <bradley.d.volkin@xxxxxxxxx>
> >
> > MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM, and MI_LOAD_REGISTER_IMM
> > commands allow userspace access to registers. Only certain registers
> > should be allowed for such access, so enable checking for those commands.
> > Each ring gets its own register whitelist.
> >
> > MI_LOAD_REGISTER_REG on HSW also allows register access but is currently
> > unused by userspace components. Leave it rejected.
> >
> > PIPE_CONTROL and MEDIA_VFE_STATE allow register access based on certain
> > bits being set. Reject those as well.
> >
> > OTC-Tracker: AXIA-4631
> > Change-Id: Ie614a2f0eb2e5917de809e5a17957175d24cc44f
> > Signed-off-by: Brad Volkin <bradley.d.volkin@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/i915_cmd_parser.c | 23 ++++++++++++++++++++---
> > drivers/gpu/drm/i915/i915_reg.h | 3 +++
> > 2 files changed, 23 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > index 296e322..5d3e303 100644
> > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > @@ -63,9 +63,12 @@ static const struct drm_i915_cmd_descriptor common_cmds[] = {
> > CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
> > CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
> > CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
> > - CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, R ),
> > - CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, R ),
> > - CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, R ),
> > + CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
> > + .reg = { .offset = 1, .mask = 0x007FFFFC } ),
> > + CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W,
> > + .reg = { .offset = 1, .mask = 0x007FFFFC } ),
> > + CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, W,
> > + .reg = { .offset = 1, .mask = 0x007FFFFC } ),
> > CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
> > };
> >
> > @@ -82,9 +85,23 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = {
> > CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
> > CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
> > CMD( PIPELINE_SELECT, S3D, F, 1, S ),
> > + CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
> > + .bits = {{
> > + .offset = 2,
> > + .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
> > + .expected = 0
> > + }},
> > + .bits_count = 1 ),
>
> From my bikeshedding dept.: here too I think it would be beneficial to
> have the count decided by an empty element, or a .valid = 1 field or
> something.
I see your point. I'll look at doing a .valid=1 or .mask!=0 check.
- Brad
>
>
> > CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
> > CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
> > CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
> > + CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
> > + .bits = {{
> > + .offset = 1,
> > + .mask = PIPE_CONTROL_MMIO_WRITE,
> > + .expected = 0
> > + }},
> > + .bits_count = 1 ),
> > };
> >
> > static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index b99bacf..6592d0d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -319,6 +319,7 @@
> > #define DISPLAY_PLANE_B (1<<20)
> > #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
> > #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
> > +#define PIPE_CONTROL_MMIO_WRITE (1<<23)
> > #define PIPE_CONTROL_CS_STALL (1<<20)
> > #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
> > #define PIPE_CONTROL_QW_WRITE (1<<14)
> > @@ -359,6 +360,8 @@
> >
> > #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
> > #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
> > +#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
> > +#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
> > #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
> > #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
> > #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
> > --
> > 1.8.5.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center
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