[snip] On Wed, Feb 05, 2014 at 07:22:33AM -0800, Jani Nikula wrote: > On Wed, 29 Jan 2014, bradley.d.volkin@xxxxxxxxx wrote: > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 13ed6ed..2b7c26e 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -339,21 +339,22 @@ > > /* > > * Commands used only by the command parser > > */ > > -#define MI_SET_PREDICATE MI_INSTR(0x01, 0) > > -#define MI_ARB_CHECK MI_INSTR(0x05, 0) > > -#define MI_RS_CONTROL MI_INSTR(0x06, 0) > > -#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) > > -#define MI_PREDICATE MI_INSTR(0x0C, 0) > > -#define MI_RS_CONTEXT MI_INSTR(0x0F, 0) > > -#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) > > -#define MI_URB_CLEAR MI_INSTR(0x19, 0) > > -#define MI_UPDATE_GTT MI_INSTR(0x23, 0) > > -#define MI_CLFLUSH MI_INSTR(0x27, 0) > > -#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) > > -#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) > > -#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) > > -#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) > > -#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) > > +#define MI_SET_PREDICATE MI_INSTR(0x01, 0) > > +#define MI_ARB_CHECK MI_INSTR(0x05, 0) > > +#define MI_RS_CONTROL MI_INSTR(0x06, 0) > > +#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) > > +#define MI_PREDICATE MI_INSTR(0x0C, 0) > > +#define MI_RS_CONTEXT MI_INSTR(0x0F, 0) > > +#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) > > +#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) > > +#define MI_URB_CLEAR MI_INSTR(0x19, 0) > > +#define MI_UPDATE_GTT MI_INSTR(0x23, 0) > > +#define MI_CLFLUSH MI_INSTR(0x27, 0) > > +#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) > > +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) > > +#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) > > +#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) > > +#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) > > Superfluous whitespace change hunk. It adds MI_LOAD_SCAN_LINES_EXCL and adjusts the whitespace to line up. I see that the whitespace change makes the actual change less obvious. I'll try to clean that up. - Brad > > > > #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) > > > > #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) > > -- > > 1.8.5.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
