On Wed, 29 Jan 2014, bradley.d.volkin@xxxxxxxxx wrote:
> From: Brad Volkin <bradley.d.volkin@xxxxxxxxx>
>
> These registers are currently used by mesa for blitting,
> transform feedback extensions, and performance monitoring
> extensions.
>
> Signed-off-by: Brad Volkin <bradley.d.volkin@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 55 ++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++++++
> 2 files changed, 75 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 88456638..18d5b05 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -185,6 +185,55 @@ static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
> { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
> };
>
> +/*
> + * Register whitelists, sorted by increasing register offset.
> + *
> + * Some registers that userspace accesses are 64 bits. The register
> + * access commands only allow 32-bit accesses. Hence, we have to include
> + * entries for both halves of the 64-bit registers.
> + */
Seems like it would be useful to have a helper macro here.
#define FOO64(addr) (addr), (addr + 4)
With a better name, hopefully. My imagination fails me now.
> +
> +static const u32 gen7_render_regs[] = {
> + HS_INVOCATION_COUNT,
> + HS_INVOCATION_COUNT + sizeof(u32),
> + DS_INVOCATION_COUNT,
> + DS_INVOCATION_COUNT + sizeof(u32),
> + IA_VERTICES_COUNT,
> + IA_VERTICES_COUNT + sizeof(u32),
> + IA_PRIMITIVES_COUNT,
> + IA_PRIMITIVES_COUNT + sizeof(u32),
> + VS_INVOCATION_COUNT,
> + VS_INVOCATION_COUNT + sizeof(u32),
> + GS_INVOCATION_COUNT,
> + GS_INVOCATION_COUNT + sizeof(u32),
> + GS_PRIMITIVES_COUNT,
> + GS_PRIMITIVES_COUNT + sizeof(u32),
> + CL_INVOCATION_COUNT,
> + CL_INVOCATION_COUNT + sizeof(u32),
> + CL_PRIMITIVES_COUNT,
> + CL_PRIMITIVES_COUNT + sizeof(u32),
> + PS_INVOCATION_COUNT,
> + PS_INVOCATION_COUNT + sizeof(u32),
> + PS_DEPTH_COUNT,
> + PS_DEPTH_COUNT + sizeof(u32),
> + GEN7_SO_NUM_PRIMS_WRITTEN(0),
> + GEN7_SO_NUM_PRIMS_WRITTEN(0) + sizeof(u32),
> + GEN7_SO_NUM_PRIMS_WRITTEN(1),
> + GEN7_SO_NUM_PRIMS_WRITTEN(1) + sizeof(u32),
> + GEN7_SO_NUM_PRIMS_WRITTEN(2),
> + GEN7_SO_NUM_PRIMS_WRITTEN(2) + sizeof(u32),
> + GEN7_SO_NUM_PRIMS_WRITTEN(3),
> + GEN7_SO_NUM_PRIMS_WRITTEN(3) + sizeof(u32),
> + GEN7_SO_WRITE_OFFSET(0),
> + GEN7_SO_WRITE_OFFSET(1),
> + GEN7_SO_WRITE_OFFSET(2),
> + GEN7_SO_WRITE_OFFSET(3),
> +};
> +
> +static const u32 gen7_blt_regs[] = {
> + BCS_SWCTRL,
> +};
> +
> #define CLIENT_MASK 0xE0000000
> #define SUBCLIENT_MASK 0x18000000
> #define MI_CLIENT 0x00000000
> @@ -313,6 +362,9 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
> ring->cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
> }
>
> + ring->reg_table = gen7_render_regs;
> + ring->reg_count = ARRAY_SIZE(gen7_render_regs);
> +
> ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
> break;
> case VCS:
> @@ -329,6 +381,9 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
> ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
> }
>
> + ring->reg_table = gen7_blt_regs;
> + ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
> +
> ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
> break;
> case VECS:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2b7c26e..b99bacf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -385,6 +385,26 @@
> #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
>
> /*
> + * Registers used only by the command parser
> + */
> +#define BCS_SWCTRL 0x22200
> +
> +#define HS_INVOCATION_COUNT 0x2300
> +#define DS_INVOCATION_COUNT 0x2308
> +#define IA_VERTICES_COUNT 0x2310
> +#define IA_PRIMITIVES_COUNT 0x2318
> +#define VS_INVOCATION_COUNT 0x2320
> +#define GS_INVOCATION_COUNT 0x2328
> +#define GS_PRIMITIVES_COUNT 0x2330
> +#define CL_INVOCATION_COUNT 0x2338
> +#define CL_PRIMITIVES_COUNT 0x2340
> +#define PS_INVOCATION_COUNT 0x2348
> +#define PS_DEPTH_COUNT 0x2350
> +
> +/* There are the 4 64-bit counter registers, one for each stream output */
> +#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
> +
> +/*
> * Reset registers
> */
> #define DEBUG_RESET_I830 0x6070
> --
> 1.8.5.2
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
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--
Jani Nikula, Intel Open Source Technology Center
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