On Tue, Feb 04, 2014 at 08:20:31PM +0200, Ville Syrjälä wrote: > On Tue, Feb 04, 2014 at 02:22:24PM +0200, Antti Koskipaa wrote: > > RFCv2: Reorganize array indexing so that full offsets can be used as > > is. It makes grepping for registers in i915_reg.h much easier. Also > > move offset arrays to intel_device_info. > > > > v1: Fixed offsets for VLV, proper eDP handling > > > > v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros. > > > > v3: Added EDP pipe comment, removed redundant offset arrays for > > MSA_MISC and DDI_FUNC_CTL. > > > > v4: Rename patch and report object size increase. > > > > v5: Change location of commas, add PIPE_EDP into enum pipe > > > > v6: Insert PIPE_EDP_OFFSET into pipe offset array > > > > v7: Set I915_MAX_PIPES back to 3, change more registers accessors > > to use the new macros, get rid of _PIPE_INC and add dev_priv > > as a parameter where required by the new macros. > > > > Upcoming hardware will not have the various display pipe register > > ranges evenly spaced in memory. Change register address calculations > > into array lookups. > > > > Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP. > > > > I left the UMS cruft untouched. > > > > Size differences: > > text data bss dec hex filename > > 596431 4634 56 601121 92c21 i915.ko (new) > > 593199 4634 56 597889 91f81 i915.ko (old) > > > > Signed-off-by: Antti Koskipaa <antti.koskipaa@xxxxxxxxxxxxxxx> > > Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > Tested-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > To elaborate a bit, I fired this up on HSW ULT w/ eDP, IVB w/ HDMI, and > 855GM w/ LVDS. I think I also tried HSW and IVB with a another HDMI > monitor plugged in, and the 855GM w/ VGA plugged in. > > As added insurance I enabled the reg_rw tracepoint and traced all the > register access we do when loading the driver (w/ fbcon enabled to get > some modesets in the trace). I compared traces between patched and > unpatched kernels and tried to see if there were any significant > differences. Couldn't spot anything apart from a few small differences > in the order of register accesses due parallel activity. Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
