Atm on VLV we handle any pending pipestat interruts, whether or not these were actually enabled explicitly with i915_enable_pipestat(). This may or may not cause any real problem, but for consistency it's worth fixing. See the last patch for more details. I also need this as a dependency for the VLV power domain support, since there we have to make sure we properly disable all pipestat interrupts during the power well is off. I've already sent the first patch separate from this set, but I include it here since it's a dependency. Tested on VLV with igt/kms_flip. Imre Deak (7): drm/i915: vlv: don't unmask IIR[DISPLAY_PIPE_A/B_VBLANK] interrupt drm/i915: factor out valleyview_pipestat_irq_handler drm/i915: vlv: s/spin_lock_irqsave/spin_lock/ in irq handler drm/i915: unify FLIP_DONE macro names drm/i915: pass status instead of enable flags to i915_enable_pipestat drm/i915: vlv: fix mapping of pipestat enable to status bits drm/i915: vlv: handle only enabled pipestat interrupt events drivers/gpu/drm/i915/i915_drv.h | 7 +- drivers/gpu/drm/i915/i915_irq.c | 218 ++++++++++++++++++++++++++-------------- drivers/gpu/drm/i915/i915_reg.h | 28 ++++-- drivers/gpu/drm/i915/intel_tv.c | 8 +- 4 files changed, 172 insertions(+), 89 deletions(-) -- 1.8.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
