Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
I think this was the last wa patch to be reviewed yet. Please let me
know if I' m still missing any.
On Wed, Jan 22, 2014 at 2:32 PM, <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Both Bspec and the W/A database state that WaDisablePSDDualDispatchEnable
> is only needed for IVB GT1.
>
> The only real confusion here is that the the W/A database also says to
> write to the GT2 only register as well, which is strange if the W/A is
> only for GT1.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 7 -------
> 1 file changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b268a55..6781845 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4828,13 +4828,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> if (IS_IVB_GT1(dev))
> I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> - else {
> - /* must write both registers */
> - I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> - _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> - I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
> - _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> - }
>
> /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
> I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> --
> 1.8.3.2
>
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--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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