On Thu, Jan 30, 2014 at 02:18:32PM +0100, Daniel Vetter wrote: > On Thu, Jan 30, 2014 at 1:46 PM, Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> wrote: > > Oh. So they changed how post-sync writes operated - this should be a > > separate fix for stable I believe (so that batches are not run before we > > have finished invalidating the TLBs required). > > We have an igt to exercise tlb invalidation stuff, which runs on all > rings. But it only runs a batch, so only uses the CS tlb. Do we need > to extend this? You could try and catch out the sampler. Or it may be that the hardware internally serialises the operation of invalidating the TLBs and lookup. Or it may be just such a slim window that it will only be hit during a demo and never a test case ;) -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
