Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> On Wed, Jan 22, 2014 at 5:32 PM, <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > WaDisableTDLUnitClockGating is only relevant for early steppings of VLV. > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_pm.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 1a45566..dd68414 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4932,7 +4932,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > * This implements the WaDisableRCZUnitClockGating:vlv workaround. > */ > I915_WRITE(GEN6_UCGCTL2, > - GEN7_TDLUNIT_CLOCK_GATE_DISABLE | > GEN6_RCZUNIT_CLOCK_GATE_DISABLE); > > /* WaDisableL3Bank2xClockGate:vlv */ > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
