Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> On Wed, Jan 22, 2014 at 5:32 PM, <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > WaDisableRCCUnitClockGating is only relevant for SNB. > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_pm.c | 6 +----- > 1 file changed, 1 insertion(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 1e1c1b1..d8381b5 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4961,9 +4961,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > * Sanctuary and Tropics, and apparently anything else with > * alpha test or pixel discard. > * > - * According to the spec, bit 11 (RCCUNIT) must also be set, > - * but we didn't debug actual testcases to find it out. > - * > * According to the spec, bit 13 (RCZUNIT) must be set on IVB. > * This implements the WaDisableRCZUnitClockGating:vlv workaround. > * > @@ -4974,8 +4971,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > GEN7_VDSUNIT_CLOCK_GATE_DISABLE | > GEN7_TDLUNIT_CLOCK_GATE_DISABLE | > GEN6_RCZUNIT_CLOCK_GATE_DISABLE | > - GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | > - GEN6_RCCUNIT_CLOCK_GATE_DISABLE); > + GEN6_RCPBUNIT_CLOCK_GATE_DISABLE); > > /* WaDisableL3Bank2xClockGate:vlv */ > I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
