Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> On Wed, Jan 22, 2014 at 5:32 PM, <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Someone copy pasted the comment from the SNB code w/o reading it. > We never actually implemented the workaround to disable RCPB unit > clock gating on IVB. It would have been needed for early steppings, > but we don't care about those anymore, so just remove the stale > comment. > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_pm.c | 8 +------- > 1 file changed, 1 insertion(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 62d339b..bf45b4c 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4849,13 +4849,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) > I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & > ~L3SQ_URB_READ_CAM_MATCH_DISABLE); > > - /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock > - * gating disable must be set. Failure to set it results in > - * flickering pixels due to Z write ordering failures after > - * some amount of runtime in the Mesa "fire" demo, and Unigine > - * Sanctuary and Tropics, and apparently anything else with > - * alpha test or pixel discard. > - * > + /* > * According to the spec, bit 13 (RCZUNIT) must be set on IVB. > * This implements the WaDisableRCZUnitClockGating:ivb workaround. > */ > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
