On Mon, Jan 27, 2014 at 11:07:06PM -0800, Ben Widawsky wrote: > v2: Rebased upon cleaned up error state > > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_drv.h | 9 ++++++++ > drivers/gpu/drm/i915/i915_gpu_error.c | 39 +++++++++++++++++++++++++++++++++++ > 2 files changed, 48 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index a144bc3..1712ecc 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -360,6 +360,14 @@ struct drm_i915_error_state { > u32 seqno; > u32 tail; > } *requests; > + > + struct { > + u32 gfx_mode; > + union { > + u64 pdp[4]; > + u32 pp_dir_base; > + }; > + } vm_info; > } ring[I915_NUM_RINGS]; > > struct drm_i915_error_buffer { > @@ -377,6 +385,7 @@ struct drm_i915_error_state { > s32 ring:4; > u32 cache_level:3; > } **active_bo, **pinned_bo; > + > u32 *active_bo_count, *pinned_bo_count; > u32 vm_count; > }; > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index 2ef0566..7fea86d 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -277,6 +277,21 @@ static void i915_ring_error_state(struct drm_i915_error_state_buf *m, > err_printf(m, " hangcheck: %s [%d]\n", > hangcheck_action_to_str(ring->hangcheck_action), > ring->hangcheck_score); > + > + if (USES_PPGTT(dev)) { > + err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); > + > + if (INTEL_INFO(dev)->gen >= 8) { > + int i; > + for (i = 0; i < 4; i++) > + err_printf(m, " PDP%d: 0x%016llx\n", > + i, ring->vm_info.pdp[i]); > + } else { > + err_printf(m, " PP_DIR_BASE: 0x%08x\n", > + ring->vm_info.pp_dir_base); > + } > + } > + Extra whitespace. I think the order here is wrong - I want to keep the "hangcheck: idle/wait/hung" as the last item in each ring block. It's one of the values I like to cross-check and so having it in a consistent position helps. Or we can put it first, perhaps inline with the ring name. Not only thank, we have all the other registers first before the software state. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx