On Wed, Jan 22, 2014 at 10:56:36AM +0200, Ville Syrjälä wrote:
> On Tue, Jan 21, 2014 at 12:42:10PM -0800, Jesse Barnes wrote:
> > Read out and calculate the port and pixel clocks on DDI configs as well.
> > This means we have to grab the DP divider values and look at the port
> > mapping to figure out which clock select reg to read out.
> >
> > v2: do the work from ddi_get_config (Ville)
> > v3: check WRPLL reference clock (Ville)
> > add additional SPLL freqs (Ville)
> > clean up port/crtc clock calc (Ville)
> > fix up crtc_clock conditionals (Ville)
> > drop superfluous dp_get_m_n from get_config (Ville)
> >
> > Signed-off-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>
>
> Look good.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Yay!
Both patches merged to dinq, thanks.
-Daniel
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 10 +++++
> > drivers/gpu/drm/i915/intel_ddi.c | 92 ++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 102 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index a699efd..7bfc710 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5306,8 +5306,12 @@
> > #define SPLL_PLL_ENABLE (1<<31)
> > #define SPLL_PLL_SSC (1<<28)
> > #define SPLL_PLL_NON_SSC (2<<28)
> > +#define SPLL_PLL_LCPLL (3<<28)
> > +#define SPLL_PLL_REF_MASK (3<<28)
> > #define SPLL_PLL_FREQ_810MHz (0<<26)
> > #define SPLL_PLL_FREQ_1350MHz (1<<26)
> > +#define SPLL_PLL_FREQ_2700MHz (2<<26)
> > +#define SPLL_PLL_FREQ_MASK (3<<26)
> >
> > /* WRPLL */
> > #define WRPLL_CTL1 0x46040
> > @@ -5318,8 +5322,13 @@
> > #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
> > /* WRPLL divider programming */
> > #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
> > +#define WRPLL_DIVIDER_REF_MASK (0xff)
> > #define WRPLL_DIVIDER_POST(x) ((x)<<8)
> > +#define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
> > +#define WRPLL_DIVIDER_POST_SHIFT 8
> > #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
> > +#define WRPLL_DIVIDER_FB_SHIFT 16
> > +#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
> >
> > /* Port clock selection */
> > #define PORT_CLK_SEL_A 0x46100
> > @@ -5332,6 +5341,7 @@
> > #define PORT_CLK_SEL_WRPLL1 (4<<29)
> > #define PORT_CLK_SEL_WRPLL2 (5<<29)
> > #define PORT_CLK_SEL_NONE (7<<29)
> > +#define PORT_CLK_SEL_MASK (7<<29)
> >
> > /* Transcoder clock selection */
> > #define TRANS_CLK_SEL_A 0x46140
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 1488b28..b6171cf 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -633,6 +633,96 @@ static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
> > /* Otherwise a < c && b >= d, do nothing */
> > }
> >
> > +static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
> > + int reg)
> > +{
> > + int refclk = LC_FREQ;
> > + int n, p, r;
> > + u32 wrpll;
> > +
> > + wrpll = I915_READ(reg);
> > + switch (wrpll & SPLL_PLL_REF_MASK) {
> > + case SPLL_PLL_SSC:
> > + case SPLL_PLL_NON_SSC:
> > + /*
> > + * We could calculate spread here, but our checking
> > + * code only cares about 5% accuracy, and spread is a max of
> > + * 0.5% downspread.
> > + */
> > + refclk = 135;
> > + break;
> > + case SPLL_PLL_LCPLL:
> > + refclk = LC_FREQ;
> > + break;
> > + default:
> > + WARN(1, "bad wrpll refclk\n");
> > + return 0;
> > + }
> > +
> > + r = wrpll & WRPLL_DIVIDER_REF_MASK;
> > + p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
> > + n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
> > +
> > + return (LC_FREQ * n) / (p * r);
> > +}
> > +
> > +static void intel_ddi_clock_get(struct intel_encoder *encoder,
> > + struct intel_crtc_config *pipe_config)
> > +{
> > + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> > + enum port port = intel_ddi_get_encoder_port(encoder);
> > + int link_clock = 0;
> > + u32 val, pll;
> > +
> > + val = I915_READ(PORT_CLK_SEL(port));
> > + switch (val & PORT_CLK_SEL_MASK) {
> > + case PORT_CLK_SEL_LCPLL_810:
> > + link_clock = 81000;
> > + break;
> > + case PORT_CLK_SEL_LCPLL_1350:
> > + link_clock = 135000;
> > + break;
> > + case PORT_CLK_SEL_LCPLL_2700:
> > + link_clock = 270000;
> > + break;
> > + case PORT_CLK_SEL_WRPLL1:
> > + link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
> > + break;
> > + case PORT_CLK_SEL_WRPLL2:
> > + link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
> > + break;
> > + case PORT_CLK_SEL_SPLL:
> > + pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
> > + if (pll == SPLL_PLL_FREQ_810MHz)
> > + link_clock = 81000;
> > + else if (pll == SPLL_PLL_FREQ_1350MHz)
> > + link_clock = 135000;
> > + else if (pll == SPLL_PLL_FREQ_2700MHz)
> > + link_clock = 270000;
> > + else {
> > + WARN(1, "bad spll freq\n");
> > + return;
> > + }
> > + break;
> > + default:
> > + WARN(1, "bad port clock sel\n");
> > + return;
> > + }
> > +
> > + pipe_config->port_clock = link_clock * 2;
> > +
> > + if (pipe_config->has_pch_encoder)
> > + pipe_config->adjusted_mode.crtc_clock =
> > + intel_dotclock_calculate(pipe_config->port_clock,
> > + &pipe_config->fdi_m_n);
> > + else if (pipe_config->has_dp_encoder)
> > + pipe_config->adjusted_mode.crtc_clock =
> > + intel_dotclock_calculate(pipe_config->port_clock,
> > + &pipe_config->dp_m_n);
> > + else
> > + pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
> > +}
> > +
> > static void
> > intel_ddi_calculate_wrpll(int clock /* in Hz */,
> > unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
> > @@ -1504,6 +1594,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
> > dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
> > }
> > +
> > + intel_ddi_clock_get(encoder, pipe_config);
> > }
> >
> > static void intel_ddi_destroy(struct drm_encoder *encoder)
> > --
> > 1.8.3.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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