> -----Original Message----- > From: intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx [mailto:intel-gfx- > bounces@xxxxxxxxxxxxxxxxxxxxx] On Behalf Of Antti Koskipaa > Sent: Wednesday, January 15, 2014 5:26 AM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Subject: [PATCH] drm/i915: Clean up display pipe register accesses > > RFCv2: Reorganize array indexing so that full offsets can be used as > is. It makes grepping for registers in i915_reg.h much easier. Also > move offset arrays to intel_device_info. > > PATCHv1: Fixed offsets for VLV, proper eDP handling > > Upcoming hardware will not have the various display pipe register > ranges evenly spaced in memory. Change register address calculations > into array lookups. > > Tested on SNB, VLV, IVB and HSW w/eDP. > > I left the UMS cruft untouched. > > Signed-off-by: Antti Koskipaa <antti.koskipaa@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_drv.c | 44 +++++++++ > drivers/gpu/drm/i915/i915_drv.h | 11 ++- > drivers/gpu/drm/i915/i915_reg.h | 191 +++++++++++++++++++++++-------- > --------- > 3 files changed, 164 insertions(+), 82 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c > b/drivers/gpu/drm/i915/i915_drv.c > index 62c0f16..3ac2ad2 100644 [snip] > +#define _HTOTAL_B 0x61000 > +#define _HBLANK_B 0x61004 > +#define _HSYNC_B 0x61008 > +#define _VTOTAL_B 0x6100c > +#define _VBLANK_B 0x61010 > +#define _VSYNC_B 0x61014 > +#define _PIPEBSRC 0x6101c > +#define _BCLRPAT_B 0x61020 > +#define _VSYNCSHIFT_B 0x61028 > + > +#define TRANSCODER_A_OFFSET 0x60000 > +#define TRANSCODER_B_OFFSET 0x61000 > +#define TRANSCODER_C_OFFSET 0x62000 > +#define TRANSCODER_EDP_OFFSET 0x6f000 > + > +#define _TRANSCODER2(pipe, reg) (dev_priv->info->trans_offsets[(pipe)] - > \ > + dev_priv->info->trans_offsets[TRANSCODER_A] + (reg) + \ > + dev_priv->info->display_mmio_offset) > + > +#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A) > +#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A) > +#define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A) > +#define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A) > +#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A) > +#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A) > +#define BCLRPAT(pipe) _PIPE2(pipe, _BCLRPAT_A) BCLRPAT is in the transcoder, not the pipe. > +#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) > > /* HSW+ eDP PSR registers */ > #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : > 0x6f800) > @@ -3173,10 +3186,10 @@ > /* Display & cursor control */ > > /* Pipe A */ > -#define _PIPEADSL (dev_priv->info->display_mmio_offset + > 0x70000) > +#define _PIPEADSL 0x70000 > #define DSL_LINEMASK_GEN2 0x00000fff > #define DSL_LINEMASK_GEN3 0x00001fff > -#define _PIPEACONF (dev_priv->info->display_mmio_offset + > 0x70008) > +#define _PIPEACONF 0x70008 > #define PIPECONF_ENABLE (1<<31) > #define PIPECONF_DISABLE 0 > #define PIPECONF_DOUBLE_WIDE (1<<30) > @@ -3219,7 +3232,7 @@ > #define PIPECONF_DITHER_TYPE_ST1 (1<<2) > #define PIPECONF_DITHER_TYPE_ST2 (2<<2) > #define PIPECONF_DITHER_TYPE_TEMP (3<<2) > -#define _PIPEASTAT (dev_priv->info->display_mmio_offset + > 0x70024) > +#define _PIPEASTAT 0x70024 > #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) > #define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30) > #define PIPE_CRC_ERROR_ENABLE (1UL<<29) > @@ -3257,12 +3270,21 @@ > #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) > #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) > > -#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) > -#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF) > -#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) > -#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, > _PIPEBFRAMEHIGH) > -#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, > _PIPEBFRAMEPIXEL) > -#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) > +#define PIPE_A_OFFSET 0x70000 > +#define PIPE_B_OFFSET 0x71000 > +#define PIPE_C_OFFSET 0x72000 > +#define PIPE_EDP_OFFSET 0x7f000 > + > +#define _PIPE2(pipe, reg) (dev_priv->info->pipe_offsets[pipe] - \ > + dev_priv->info->pipe_offsets[PIPE_A] + (reg) + \ > + dev_priv->info->display_mmio_offset) > + > +#define PIPESRC(pipe) _PIPE2(pipe, _PIPEASRC) PIPERSRC is in the transcoder not in the pipe. > +#define PIPECONF(tran) _TRANSCODER2(tran, _PIPEACONF) PIPECONF is in the pipe not the transcoder. > +#define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL) > +#define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH) > +#define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL) > +#define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT) > [snip] Missing from that patch is also all the DSP* registers (DSPCNTR,DSPADDR, etc...) those should use the new _PIPE2 macro. Thanks, Rafael _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
