On Tue, Jan 21, 2014 at 10:22:31AM -0700, Todd Previte wrote: > These bits are in reverse order in the header from those defined in > the specification. Change the bit positions for ports B and D to > correctly match the spec. > > - Added sign-off > > Signed-off-by: Todd Previte <tprevite@xxxxxxxxx> > > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 10ecf90..2d77b51 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2083,9 +2083,9 @@ > * Please check the detailed lore in the commit message for for experimental > * evidence. > */ > -#define PORTD_HOTPLUG_LIVE_STATUS (1 << 29) > +#define PORTD_HOTPLUG_LIVE_STATUS (1 << 27) > #define PORTC_HOTPLUG_LIVE_STATUS (1 << 28) > -#define PORTB_HOTPLUG_LIVE_STATUS (1 << 27) > +#define PORTB_HOTPLUG_LIVE_STATUS (1 << 29) As Jani explained, this will break g4x. And it might very well be that this particular lie has been carried forward until baytrail, so I think we must cross check Bspec first with the reality of shipping platforms. -Daniel > #define PORTD_HOTPLUG_INT_STATUS (3 << 21) > #define PORTC_HOTPLUG_INT_STATUS (3 << 19) > #define PORTB_HOTPLUG_INT_STATUS (3 << 17) > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
