On Thu, Dec 19, 2013 at 09:39:12AM -0800, Jesse Barnes wrote: > On Thu, 19 Dec 2013 14:29:44 -0200 > Paulo Zanoni <przanoni@xxxxxxxxx> wrote: > > > From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> > > > > Because we already do the wait in software: see > > ironlake_wait_backlight_on and ironlake_edp_wait_backlight_off. > > > > For the "backlight on" delay, even BSpec says we need to program 0x1 > > to PP_ON_DELAYS 12:0. > > > > For the "backlight off" delay, if we don't do the same thing, when we > > call ironlake_wait_panel_off we'll end up waiting for the it again. > > > > On my machine the off delay is 200ms, so we save this amount of time > > whenever we disable the panel (e.g, suspend). > > > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> > > --- > > drivers/gpu/drm/i915/intel_dp.c | 13 ++++++++++--- > > 1 file changed, 10 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > index 69d8f1c..90ff059 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -3535,10 +3535,17 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, > > pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); > > } > > > > - /* And finally store the new values in the power sequencer. */ > > + /* > > + * And finally store the new values in the power sequencer. The > > + * backlight delays are set to 1 because we do manual waits on them. For > > + * T8, even BSpec recommends doing it. For T9, if we don't do this, > > + * we'll end up waiting for the backlight off delay twice: once when we > > + * do the manual sleep, and once when we disable the panel and wait for > > + * the PP_STATUS bit to become zero. > > + */ > > pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | > > - (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); > > - pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | > > + (1 << PANEL_LIGHT_ON_DELAY_SHIFT); > > + pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | > > (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); > > /* Compute the divisor for the pp clock, simply match the Bspec > > * formula. */ > > Yay! > > Reviewed-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> I'll wait with this one until the updated version of patch 3 is finalized, but I've meanwhile pulled in patches 4&5. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
