>Please use the symbolic constants in i915_reg.h, we can reuse the ones below GEN6_PMIER. Also Chris had some comment to move this code around, but I didn't really understand what he wants. Chris, can you please clarify? Hi Chris, Can you please clarify on this? Thanks Deepak -----Original Message----- From: Daniel Vetter [mailto:daniel.vetter@xxxxxxxx] On Behalf Of Daniel Vetter Sent: Tuesday, January 14, 2014 2:52 PM To: S, Deepak Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; Chris Wilson Subject: Re: [PATCH v3 1/3] drm/i915: Disable/Enable PM Intrrupts based on the current freq. On Thu, Jan 09, 2014 at 07:31:08PM +0530, deepak.s@xxxxxxxxx wrote: > From: Deepak S <deepak.s@xxxxxxxxx> > > When current delay is already at max delay, Let's disable the PM UP > THRESHOLD INTRRUPTS, so that we will not get further interrupts until > current delay is less than max delay, Also request for the PM DOWN > THRESHOLD INTRRUPTS to indicate the decrease in clock freq. and > viceversa for PM DOWN THRESHOLD INTRRUPTS. > > v2: Use bool variables (Daniel) > > v3: Fix Interrupt masking bit (Deepak) > > Signed-off-by: Deepak S <deepak.s@xxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_drv.h | 3 +++ > drivers/gpu/drm/i915/i915_irq.c | 31 +++++++++++++++++++++++++++++-- > drivers/gpu/drm/i915/intel_pm.c | 3 +++ > 3 files changed, 35 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > b/drivers/gpu/drm/i915/i915_drv.h index cc8afff..d49e674 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -943,6 +943,9 @@ struct intel_gen6_power_mgmt { > u8 rp0_delay; > u8 hw_max; > > + bool rp_up_masked; > + bool rp_down_masked; > + > int last_adj; > enum { LOW_POWER, BETWEEN, HIGH_POWER } power; > > diff --git a/drivers/gpu/drm/i915/i915_irq.c > b/drivers/gpu/drm/i915/i915_irq.c index 1d44c79..e87d47a 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -988,7 +988,20 @@ static void gen6_pm_rps_work(struct work_struct *work) > adj *= 2; > else > adj = 1; > - new_delay = dev_priv->rps.cur_delay + adj; > + > + if (dev_priv->rps.cur_delay >= dev_priv->rps.max_delay) { > + I915_WRITE(GEN6_PMINTRMSK, > + I915_READ(GEN6_PMINTRMSK) | 1 << 5); Please use the symbolic constants in i915_reg.h, we can reuse the ones below GEN6_PMIER. Also Chris had some comment to move this code around, but I didn't really understand what he wants. Chris, can you please clarify? Thanks, Daniel > + dev_priv->rps.rp_up_masked = true; > + new_delay = dev_priv->rps.cur_delay; > + } else > + new_delay = dev_priv->rps.cur_delay + adj; > + > + if (dev_priv->rps.rp_down_masked) { > + I915_WRITE(GEN6_PMINTRMSK, > + I915_READ(GEN6_PMINTRMSK) & ~(1 << 4)); > + dev_priv->rps.rp_down_masked = false; > + } > > /* > * For better performance, jump directly @@ -1007,7 +1020,21 @@ > static void gen6_pm_rps_work(struct work_struct *work) > adj *= 2; > else > adj = -1; > - new_delay = dev_priv->rps.cur_delay + adj; > + > + if (dev_priv->rps.cur_delay <= dev_priv->rps.min_delay) { > + I915_WRITE(GEN6_PMINTRMSK, > + I915_READ(GEN6_PMINTRMSK) | 1 << 4); > + dev_priv->rps.rp_down_masked = true; > + new_delay = dev_priv->rps.cur_delay; > + } else > + new_delay = dev_priv->rps.cur_delay + adj; > + > + if (dev_priv->rps.rp_up_masked) { > + I915_WRITE(GEN6_PMINTRMSK, > + I915_READ(GEN6_PMINTRMSK) & ~(1 << 5)); > + dev_priv->rps.rp_up_masked = false; > + } > + > } else { /* unknown event */ > new_delay = dev_priv->rps.cur_delay; > } > diff --git a/drivers/gpu/drm/i915/intel_pm.c > b/drivers/gpu/drm/i915/intel_pm.c index 469170c..9c950e4 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3628,6 +3628,9 @@ static void valleyview_enable_rps(struct drm_device *dev) > vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay), > dev_priv->rps.rpe_delay); > > + dev_priv->rps.rp_up_masked = false; > + dev_priv->rps.rp_down_masked = false; > + > valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); > > gen6_enable_rps_interrupts(dev); > -- > 1.8.4.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
