On Wed, Jan 08, 2014 at 05:26:31PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
>
> The WA is mentioned in HSW's GAMMA_MODE register documentation, but
> not on on BDW's documentation, so let's assume it is not needed there.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
It looks that way indeed (not tested either).
Reviewed-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
--
Damien
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Not tested.
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index bf4c6b5..3d98bcd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3496,7 +3496,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
> /* Workaround : Do not read or write the pipe palette/gamma data while
> * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> */
> - if (intel_crtc->config.ips_enabled &&
> + if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
> ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
> GAMMA_MODE_MODE_SPLIT)) {
> hsw_disable_ips(intel_crtc);
> --
> 1.8.4.2
>
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