From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
I started to think a bit about how the code should look for doing a full
modeset for more than one pipe at a time. This is how far I got yesterday.
I suppose the next thing would be moving the PLL calculations into compute
config stage, and then actually computing a new pipe config for more than
one pipe.
After that we could improve the IVB bifurcate stuff to handle cases where
pipe B is already enabled w/ > 2 FDI lanes, and then we try to light up
pipe C. Assuming pipe B bandwidth can be reduced sufficiently to fit into
two lanes, such an operation should succeed.
But I think I'll try to finish off some of my other pending stuff before
I continue with this.
I fired this up on an IVB briefly and things seem fine. I didn't actually
test the VLV cdclk change due to lack of hardware.
Ville Syrjälä (4):
drm/i915: Pre-compute pipe enabled state
drm/i915: Prepare to track new pipe config per pipe
drm/i915: Use new_config and new_enabled to simplify the VLV cdclk
code
drm/i915: Don't oops if the initial modeset fails
drivers/gpu/drm/i915/intel_display.c | 140 +++++++++++++++++++++++++++--------
drivers/gpu/drm/i915/intel_drv.h | 3 +
2 files changed, 111 insertions(+), 32 deletions(-)
--
1.8.3.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
