On Tue, Dec 17, 2013 at 10:52:24PM +0200, Imre Deak wrote: > VGA detection requires the reference clock to be on, so make sure this > is the case. > > This fixes VGA hotplug/manual detection where all pipes are off and so > we would normally disable all clocks. > > v2: > - Instead of disabling PSR clock gating, force the reference clock on > through the DPLL_A register. (Kin Chan S <kin.s.chan@xxxxxxxxx>) > > Reported-by: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++++-- > drivers/gpu/drm/i915/intel_pm.c | 5 +++++ > 2 files changed, 17 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 674fd43..f3a0a7e 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1507,9 +1507,15 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) > /* Make sure the pipe isn't still relying on us */ > assert_pipe_disabled(dev_priv, pipe); > > - /* Leave integrated clock source enabled */ > + /* > + * Leave integrated clock source enabled for pipe B and the reference > + * clock for pipe A. The latter is needed for VGA hotplug / manual > + * detection. > + */ > if (pipe == PIPE_B) > val = DPLL_INTEGRATED_CRI_CLK_VLV; > + else > + val = DPLL_REFA_CLK_ENABLE_VLV; > I915_WRITE(DPLL(pipe), val); > POSTING_READ(DPLL(pipe)); > } > @@ -4984,7 +4990,11 @@ static void vlv_update_pll(struct intel_crtc *crtc) > > vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); > > - /* Enable DPIO clock input */ > + /* > + * Enable DPIO clock input. We should never disable the reference > + * clock for pipe A, since VGA hotplug / manual detection depends > + * on it. Set it here for state tracking. > + */ > dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | > DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; > /* We should never disable this, set it here for state tracking */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index fccd7a8..1c1de83 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4933,6 +4933,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > > I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); > > + /* Force the reference clock on for VGA hotplug / manual detection */ > + val = I915_READ(DPLL(PIPE_A)); > + val |= DPLL_REFA_CLK_ENABLE_VLV; > + I915_WRITE(DPLL(PIPE_A), val); > + Maybe put this part into intel_init_dpio()? I can't really comment on the rest since I have no idea why it works. > /* WaDisableEarlyCull:vlv */ > I915_WRITE(_3D_CHICKEN3, > _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); > -- > 1.8.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
