According to Art, we don't have a way to read back the state reliably at runtime, at least not without risking disabling it again. So drop the readout and checking on BDW. References: https://bugs.freedesktop.org/show_bug.cgi?id=71906 Signed-off-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/intel_display.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4d1357a..b6dfae6 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7004,8 +7004,9 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, if (intel_display_power_enabled(dev, pfit_domain)) ironlake_get_pfit_config(crtc, pipe_config); - pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && - (I915_READ(IPS_CTL) & IPS_ENABLE); + if (IS_HASWELL(dev)) + pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && + (I915_READ(IPS_CTL) & IPS_ENABLE); pipe_config->pixel_multiplier = 1; @@ -9335,7 +9336,9 @@ intel_pipe_config_compare(struct drm_device *dev, PIPE_CONF_CHECK_I(pch_pfit.size); } - PIPE_CONF_CHECK_I(ips_enabled); + /* BDW+ don't expose a synchronous way to read the state */ + if (IS_HASWELL(dev)) + PIPE_CONF_CHECK_I(ips_enabled); PIPE_CONF_CHECK_I(double_wide); -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
