While the longer goal is to have dev_priv == dev by properly subclassing
struct drm_device, quite a few macros in i915_drv.h need the dev
argument. Let's not try to disrupt everything yet and just remove their
usage of INTEL_INFO() as a first step.
Signed-off-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_drv.h | 81 +++++++++++++++++++++--------------------
1 file changed, 41 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cc8afff..e9c3339 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -156,7 +156,8 @@ enum hpd_pin {
I915_GEM_DOMAIN_INSTRUCTION | \
I915_GEM_DOMAIN_VERTEX)
-#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
+#define for_each_pipe(p) \
+ for ((p) = 0; (p) < to_i915(dev)->info->num_pipes; (p)++)
#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
@@ -1775,32 +1776,32 @@ struct drm_i915_file_private {
#define IS_I830(dev) ((dev)->pdev->device == 0x3577)
#define IS_845G(dev) ((dev)->pdev->device == 0x2562)
-#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
+#define IS_I85X(dev) (to_i915(dev)->info->is_i85x)
#define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
-#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
+#define IS_I915G(dev) (to_i915(dev)->info->is_i915g)
#define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
#define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
-#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
-#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
-#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
+#define IS_I945GM(dev) (to_i915(dev)->info->is_i945gm)
+#define IS_BROADWATER(dev) (to_i915(dev)->info->is_broadwater)
+#define IS_CRESTLINE(dev) (to_i915(dev)->info->is_crestline)
#define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
-#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
+#define IS_G4X(dev) (to_i915(dev)->info->is_g4x)
#define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
#define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
-#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
-#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
+#define IS_PINEVIEW(dev) (to_i915(dev)->info->is_pineview)
+#define IS_G33(dev) (to_i915(dev)->info->is_g33)
#define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
-#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
+#define IS_IVYBRIDGE(dev) (to_i915(dev)->info->is_ivybridge)
#define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
(dev)->pdev->device == 0x0152 || \
(dev)->pdev->device == 0x015a)
#define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
(dev)->pdev->device == 0x0106 || \
(dev)->pdev->device == 0x010A)
-#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
-#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
-#define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8)
-#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
+#define IS_VALLEYVIEW(dev) (to_i915(dev)->info->is_valleyview)
+#define IS_HASWELL(dev) (to_i915(dev)->info->is_haswell)
+#define IS_BROADWELL(dev) (to_i915(dev)->info->gen == 8)
+#define IS_MOBILE(dev) (to_i915(dev)->info->is_mobile)
#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
((dev)->pdev->device & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
@@ -1820,33 +1821,33 @@ struct drm_i915_file_private {
* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
* chips, etc.).
*/
-#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
-#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
-#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
-#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
-#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
-#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
-#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
+#define IS_GEN2(dev) (to_i915(dev)->info->gen == 2)
+#define IS_GEN3(dev) (to_i915(dev)->info->gen == 3)
+#define IS_GEN4(dev) (to_i915(dev)->info->gen == 4)
+#define IS_GEN5(dev) (to_i915(dev)->info->gen == 5)
+#define IS_GEN6(dev) (to_i915(dev)->info->gen == 6)
+#define IS_GEN7(dev) (to_i915(dev)->info->gen == 7)
+#define IS_GEN8(dev) (to_i915(dev)->info->gen == 8)
#define RENDER_RING (1<<RCS)
#define BSD_RING (1<<VCS)
#define BLT_RING (1<<BCS)
#define VEBOX_RING (1<<VECS)
-#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
-#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
-#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
-#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
+#define HAS_BSD(dev) (to_i915(dev)->info->ring_mask & BSD_RING)
+#define HAS_BLT(dev) (to_i915(dev)->info->ring_mask & BLT_RING)
+#define HAS_VEBOX(dev) (to_i915(dev)->info->ring_mask & VEBOX_RING)
+#define HAS_LLC(dev) (to_i915(dev)->info->has_llc)
#define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
-#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
+#define I915_NEED_GFX_HWS(dev) (to_i915(dev)->info->need_gfx_hws)
-#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
-#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
-#define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_BROADWELL(dev))
+#define HAS_HW_CONTEXTS(dev) (to_i915(dev)->info->gen >= 6)
+#define HAS_ALIASING_PPGTT(dev) (to_i915(dev)->info->gen >= 6 && !IS_VALLEYVIEW(dev))
+#define HAS_PPGTT(dev) (to_i915(dev)->info->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_BROADWELL(dev))
#define USES_ALIASING_PPGTT(dev) intel_enable_ppgtt(dev, false)
#define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
-#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
-#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
+#define HAS_OVERLAY(dev) (to_i915(dev)->info->has_overlay)
+#define OVERLAY_NEEDS_PHYSICAL(dev) (to_i915(dev)->info->overlay_needs_physical)
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
@@ -1859,17 +1860,17 @@ struct drm_i915_file_private {
#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
-#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
-#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
+#define SUPPORTS_TV(dev) (to_i915(dev)->info->supports_tv)
+#define I915_HAS_HOTPLUG(dev) (to_i915(dev)->info->has_hotplug)
-#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
-#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
-#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
+#define HAS_FW_BLC(dev) (to_i915(dev)->info->gen > 2)
+#define HAS_PIPE_CXSR(dev) (to_i915(dev)->info->has_pipe_cxsr)
+#define I915_HAS_FBC(dev) (to_i915(dev)->info->has_fbc)
#define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
-#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
-#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
+#define HAS_DDI(dev) (to_i915(dev)->info->has_ddi)
+#define HAS_FPGA_DBG_UNCLAIMED(dev) (to_i915(dev)->info->has_fpga_dbg)
#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
#define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
#define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev))
@@ -2297,7 +2298,7 @@ void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
int i915_gem_gtt_init(struct drm_device *dev);
static inline void i915_gem_chipset_flush(struct drm_device *dev)
{
- if (INTEL_INFO(dev)->gen < 6)
+ if (to_i915(dev)->info->gen < 6)
intel_gtt_chipset_flush();
}
int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
@@ -2311,7 +2312,7 @@ static inline bool intel_enable_ppgtt(struct drm_device *dev, bool full)
#ifdef CONFIG_INTEL_IOMMU
/* Disable ppgtt on SNB if VT-d is on. */
- if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
+ if (to_i915(dev)->info->gen == 6 && intel_iommu_gfx_mapped) {
DRM_INFO("Disabling PPGTT because VT-d is on\n");
return false;
}
--
1.8.3.1
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