On Mon, Dec 16, 2013 at 08:50:45PM -0800, Ben Widawsky wrote: > Semaphore waits use a new instruction, MI_SEMAPHORE_WAIT. The seqno to > wait on is all well defined by the table in the previous patch. There is > nothing else different from previous GEN's semaphore synchronization > code. > > v2: Update macros to not require the other ring's ring->id (Chris) > > Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx> > --- > +/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to > + * do the writes, and that must have qw aligned offsets, simply pretend it's 8b. > + */ > +#define i915_semaphore_seqno_size sizeof(uint64_t) > +#define GEN8_SIGNAL_OFFSET(to) \ > + (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ > + (ring->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \ > + (i915_semaphore_seqno_size * (to))) > + > +#define GEN8_WAIT_OFFSET(__ring, from) \ > + (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ > + ((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \ > + (i915_semaphore_seqno_size * (__ring)->id)) Please sir, may I have #define GEN8_SEMAPHORE_OFFSET(from, to) \ (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ ((from) * I915_NUM_RINGS + (to)) * i915_semaphore_seqno_size) #define GEN8_SIGNAL_OFFSET(to) GEN8_SEMAPHORE_OFFSET(ring->id, to) #define GEN8_WAIT_OFFSET(from) GEN8_SEMAPHORE_OFFSET(from, ring->id) ? -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
