On Tue, Dec 17, 2013 at 10:58:27AM +0530, Vandana Kannan wrote:
> For Broadwell, there is one instance of Transcoder MN values per transcoder.
> For dynamic switching between multiple refreshr rates, M/N values may be
> reprogrammed on the fly. Link N programming triggers update of all data and
> link M & N registers and the new M/N values will be used in the next frame
> that is output.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@xxxxxxxxx>
> Signed-off-by: Pradeep Bhat <pradeep.bhat@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 23 +++++++++++++++++++----
> 1 file changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 209be3c..183cfd7 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -798,9 +798,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
> struct drm_i915_private *dev_priv = dev->dev_private;
> enum transcoder transcoder = crtc->config.cpu_transcoder;
>
> - if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) {
> + if (INTEL_INFO(dev)->gen >= 8) {
> + I915_WRITE(PIPE_DATA_M1(transcoder),
> + TU_SIZE(m_n->tu) | m_n->gmch_m);
> + I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
> + I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
> + I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
> + } else if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) {
Ouch. Double ouch later.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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