On Thu, 17 Oct 2013 22:53:16 +0300 ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Group the sprite register writes a bit tighter. We want to write > the registers atomically, and so doing the base address/offset > artihmetic within the critical section is pointless when it can > all be done beforehand. > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_sprite.c | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c > index 0aa5911..c160e4f 100644 > --- a/drivers/gpu/drm/i915/intel_sprite.c > +++ b/drivers/gpu/drm/i915/intel_sprite.c > @@ -118,9 +118,6 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, > crtc_w--; > crtc_h--; > > - I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); > - I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); > - > linear_offset = y * fb->pitches[0] + x * pixel_size; > sprsurf_offset = intel_gen4_compute_page_offset(&x, &y, > obj->tiling_mode, > @@ -128,6 +125,9 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, > fb->pitches[0]); > linear_offset -= sprsurf_offset; > > + I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); > + I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); > + > if (obj->tiling_mode != I915_TILING_NONE) > I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); > else > @@ -295,15 +295,15 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, > } else > dev_priv->sprite_scaling_enabled &= ~(1 << pipe); > > - I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); > - I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); > - > linear_offset = y * fb->pitches[0] + x * pixel_size; > sprsurf_offset = > intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, > pixel_size, fb->pitches[0]); > linear_offset -= sprsurf_offset; > > + I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); > + I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); > + > /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET > * register */ > if (IS_HASWELL(dev)) > @@ -473,15 +473,15 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, > if (crtc_w != src_w || crtc_h != src_h) > dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; > > - I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); > - I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); > - > linear_offset = y * fb->pitches[0] + x * pixel_size; > dvssurf_offset = > intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, > pixel_size, fb->pitches[0]); > linear_offset -= dvssurf_offset; > > + I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); > + I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); > + > if (obj->tiling_mode != I915_TILING_NONE) > I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); > else Reviewed-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
