On Wed, Dec 11, 2013 at 05:52:05PM +0530, Shobhit Kumar wrote: > Basically ULPS handling during enable/disable has been moved to > pre_enable and post_disable phases. PLL and panel power disable > also has been moved to post_disable phase. The ULPS entry/exit > sequneces as suggested by HW team is as follows - > > During enable time - > set DEVICE_READY --> Clear DEVICE_READY --> set DEVICE_READY > > And during disable time to flush all FIFOs - > set ENTER_SLEEP --> EXIT_SLEEP --> ENTER_SLEEP > > Also during disbale sequnece sub-encoder disable is moved to the end > after port is disabled. > > v2: Based on comments from Ville > - Detailed epxlaination in the commit messgae > - Moved parameter changes out into another patch > - Backlight enabling will be a new patch > > v3: Updated as per Jani's comments > - Removed the I915_WRITE_BITS as it is not needed > - Moved panel_reset and send_otp_cmds hooks to dsi_pre_enable > - Moved disable_panel_power hook to dsi_post_disable > - Replace hardcoding with AFE_LATCHOUT > > v4: Make intel_dsi_device_ready and intel_dsi_clear_device_ready static > > Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@xxxxxxxxx> > Signed-off-by: Shobhit Kumar <shobhit.kumar@xxxxxxxxx> > Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx> Merged all patches from this series, thanks. btw, when resending individual patches pls use the --in-reply-to option so that they're all nicely grouped together with the discussion. Thanks, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
