There appear to be some gen2 machines that don't really like the current PLL
limits we have. We also have some accuracy problems with the PLL calculations.
This series aims to eliminate those problems, and at least my 855 machine
seems happier with these patches.
Ville Syrjälä (5):
drm/i915: Extract p2 divider correctly for gen2 LVDS dual channel
drm/i915: Change N divider minimum from 3 to 2 for gen2
drm/i915: Increase gen2 vco frequency limit to 1512 MHz
drm/i915: Fix 66 MHz LVDS SSC freq for gen2
drm/i915: Decrease gen2 vco frequency minimum to 908 MHz
drivers/gpu/drm/i915/intel_bios.c | 8 ++++----
drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++---------------
2 files changed, 23 insertions(+), 19 deletions(-)
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